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2026-04-18 - 05:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Sat Apr 18, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2828622235175,19sleep70-21swapper/719:06:047
2829332233173,19sleep40-21swapper/419:07:054
2829072226171,18sleep50-21swapper/519:06:415
2850672219166,18sleep10-21swapper/119:09:511
2828952212183,19sleep20-21swapper/219:06:312
2849972210180,19sleep60-21swapper/619:08:516
2849942209181,18sleep30-21swapper/319:08:493
2828462209182,17sleep00-21swapper/019:05:480
285483993534,1cyclictest1-21systemd19:30:022
285490993228,3cyclictest395445-21dump-pmu-power22:30:004
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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