You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-08-26 - 21:47
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Tue Aug 26, 2025 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26655552231170,20sleep60-21swapper/607:07:556
26655122231178,18sleep10-21swapper/107:07:181
26654792225168,17sleep40-21swapper/407:06:494
26655072224173,16sleep50-21swapper/507:07:145
26634202224171,17sleep00-21swapper/007:05:080
26634742219166,17sleep70-21swapper/707:05:557
26655602216186,19sleep20-21swapper/207:07:592
26634412211183,17sleep30-21swapper/307:05:273
2666072993226,5cyclictest2775663-21dump-pmu-power10:30:005
266606299320,31cyclictest2802594-21sh11:20:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional