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2026-05-02 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Sat May 02, 2026 00:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40266752230171,48sleep50-21swapper/519:09:595
40265472226166,18sleep70-21swapper/719:08:077
40264992214180,22sleep60-21swapper/619:07:276
40264472213184,19sleep10-21swapper/119:06:411
40265962207174,21sleep20-21swapper/219:08:512
40264932206176,20sleep00-21swapper/019:07:200
40263642205175,20sleep40-21swapper/419:05:324
40265322203170,20sleep30-21swapper/319:07:563
402689199400,32cyclictest856-21dbus-daemon19:15:023
402689999340,6cyclictest374-21systemd-journal19:20:006
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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