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2025-12-28 - 07:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Sun Dec 28, 2025 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38864232242181,20sleep50-21swapper/519:07:305
38884742237180,18sleep70-21swapper/719:09:097
38864652224168,19sleep10-21swapper/119:08:051
38884222219166,18sleep20-21swapper/219:08:302
38884882214185,19sleep30-21swapper/319:09:203
38864022214187,17sleep40-21swapper/419:07:124
38863802210165,15sleep00-21swapper/019:06:530
38863302210182,18sleep60-21swapper/619:06:106
388878199320,1cyclictest0-21swapper/720:20:027
3888781993126,4cyclictest681-21dbus-daemon21:40:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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