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2026-03-03 - 18:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Tue Mar 03, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25122532241174,21sleep70-21swapper/707:05:507
25123932236179,18sleep40-21swapper/407:07:484
25122512229174,44sleep50-21swapper/507:05:485
25122462224168,18sleep00-21swapper/007:05:430
25123732220167,18sleep30-21swapper/307:07:313
25122472219166,17sleep10-21swapper/107:05:431
25143842217184,21sleep20-21swapper/207:08:332
25122792216187,18sleep60-21swapper/607:06:136
251471799524,24cyclictest0-21swapper/310:36:383
251472399340,28cyclictest0-21swapper/512:38:045
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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