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2026-02-24 - 17:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Tue Feb 24, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19152622234177,19sleep50-21swapper/519:05:595
19173722231174,19sleep00-21swapper/019:08:260
19152982231177,42sleep30-21swapper/319:06:293
19152502231160,16sleep20-21swapper/219:05:482
19152082226169,45sleep10-21swapper/119:05:141
19174802223166,18sleep40-21swapper/419:10:004
19153862222163,18sleep70-21swapper/719:07:457
19152902208180,18sleep60-21swapper/619:06:236
1917720993428,5cyclictest0-21swapper/023:10:010
191773199330,0cyclictest0-21swapper/420:20:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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