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2026-02-10 - 16:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Tue Feb 10, 2026 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194856724170,4sleep5671rcuc/507:08:175
19465632232171,48sleep40-21swapper/407:06:164
19486652231170,20sleep70-21swapper/707:08:377
19464862228170,19sleep10-21swapper/107:05:101
19465392227172,18sleep00-21swapper/007:05:570
19487112226170,19sleep60-21swapper/607:09:176
19466762213183,19sleep30-21swapper/307:07:533
19465052213183,19sleep20-21swapper/207:05:272
20762572610,0sleep30-21swapper/311:03:113
194899099370,36cyclictest0-21swapper/109:20:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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