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2026-05-23 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot4.osadl.org (updated Sat May 23, 2026 00:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16339742248182,19sleep40-21swapper/419:06:094
16340822225163,19sleep20-21swapper/219:07:442
16341122220164,45sleep30-21swapper/319:08:093
16341052215186,19sleep70-21swapper/719:08:057
16341982214184,19sleep60-21swapper/619:09:256
16340942213184,19sleep50-21swapper/519:07:555
16339502210181,19sleep00-21swapper/019:05:490
16341462209180,19sleep10-21swapper/119:08:381
1634461993635,1cyclictest1703009-21lspci21:09:287
1634457993530,4cyclictest1740111-21sqv22:15:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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