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2026-02-16 - 05:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Mon Feb 16, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38721902227170,19sleep60-21swapper/619:09:176
38700492223166,19sleep10-21swapper/119:06:221
38721662220189,20sleep20-21swapper/219:08:562
38701002220167,18sleep50-21swapper/519:07:075
38722282214185,19sleep70-21swapper/719:09:507
38700992214187,17sleep40-21swapper/419:07:064
38701442213183,19sleep30-21swapper/319:07:463
38721342212181,19sleep00-21swapper/019:08:300
387247099340,34cyclictest0-21swapper/123:40:011
387246799330,31cyclictest3938156-21sh21:10:020
387247099320,31cyclictest0-21swapper/119:30:011
3872486993127,3cyclictest4000336-21sh23:05:016
3872476993127,3cyclictest3992001-21turbostat.cron22:50:013
387247499310,30cyclictest3883796-21idleruntime-cro19:30:012
387247099310,30cyclictest3886477-21sh19:35:001
3872467993128,2cyclictest369-21systemd-journal20:45:010
387246799310,30cyclictest3986604-21sh22:40:010
387248899300,29cyclictest3991998-21idleruntime-cro22:50:007
387248899300,1cyclictest3973781-21apt-get22:18:067
387248699300,2cyclictest3962379-21apt21:55:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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