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2026-06-29 - 06:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Sun Jun 28, 2026 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13396022229170,19sleep10-21swapper/107:08:001
13396022229170,19sleep10-21swapper/107:08:001
13397362225167,47sleep20-21swapper/207:09:542
13397362225167,47sleep20-21swapper/207:09:542
13395162222173,38sleep70-21swapper/707:06:457
13395162222173,38sleep70-21swapper/707:06:457
13394852217159,18sleep50-21swapper/507:06:195
13394852217159,18sleep50-21swapper/507:06:195
13395122212183,19sleep30-21swapper/307:06:413
13395122212183,19sleep30-21swapper/307:06:413
13396142211180,20sleep40-21swapper/407:08:114
13396142211180,20sleep40-21swapper/407:08:114
13396812210182,18sleep60-21swapper/607:09:106
13396812210182,18sleep60-21swapper/607:09:106
13395362204174,20sleep00-21swapper/007:07:030
13395362204174,20sleep00-21swapper/007:07:030
133996599380,33cyclictest1447318-21cron10:25:017
133995399380,4cyclictest1458900-21chrt10:45:022
133996599350,29cyclictest856-21dbus-daemon11:00:017
133995399350,3cyclictest1450112-21cron10:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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