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2026-01-23 - 00:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Thu Jan 22, 2026 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
352112253192,49sleep40-21swapper/407:09:544
331182230174,18sleep00-21swapper/007:07:420
329452224167,19sleep50-21swapper/507:05:135
351422222168,19sleep10-21swapper/107:08:551
330262222187,22sleep30-21swapper/307:06:243
351522214182,20sleep20-21swapper/207:09:042
330772213184,18sleep70-21swapper/707:07:097
329462213185,18sleep60-21swapper/607:05:146
3563099541,25cyclictest0-21swapper/710:47:127
3563099541,25cyclictest0-21swapper/710:47:127
1196062460,0sleep30-21swapper/309:43:193
35618993939,0cyclictest0-21swapper/408:15:004
3562699370,31cyclictest180419-21apt-get11:48:116
3562699360,35cyclictest0-21swapper/609:25:226
3560199332,30cyclictest148104-21sh10:40:010
3560199332,30cyclictest148104-21sh10:40:000
35630993228,3cyclictest700-21rs:main7
35623993228,3cyclictest126299-21latency_hist10:00:015
3561899310,30cyclictest92822-21debian-sa108:55:014
3561899310,30cyclictest131691-21sh10:10:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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