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2026-06-25 - 04:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Thu Jun 25, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32877152224163,20sleep30-21swapper/319:09:583
32877152224163,20sleep30-21swapper/319:09:583
32874572223169,17sleep10-21swapper/119:06:171
32874572223169,17sleep10-21swapper/119:06:171
32875922219190,19sleep60-21swapper/619:08:166
32875922219190,19sleep60-21swapper/619:08:166
32875412216187,19sleep20-21swapper/219:07:312
32875412216187,19sleep20-21swapper/219:07:312
32875932213183,19sleep70-21swapper/719:08:177
32875932213183,19sleep70-21swapper/719:08:177
32874292212184,19sleep00-21swapper/019:05:520
32874292212184,19sleep00-21swapper/019:05:520
32875552208180,18sleep50-21swapper/519:07:425
32875552208180,18sleep50-21swapper/519:07:425
32874422203175,19sleep40-21swapper/419:06:044
32874422203175,19sleep40-21swapper/419:06:044
3287929993531,3cyclictest3322068-21cron20:10:010
328792999350,1cyclictest0-21swapper/021:10:010
3287950993433,1cyclictest17850irq/4-ttyS021:15:017
328795099343,30cyclictest17850irq/4-ttyS021:35:017
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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