You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-03 - 12:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Tue Mar 03, 2026 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7831072222167,18sleep50-21swapper/519:07:405
7830702218188,20sleep60-21swapper/619:07:096
7830762214179,22sleep30-21swapper/319:07:143
7830262214187,17sleep70-21swapper/719:06:297
7829722213186,17sleep00-21swapper/019:05:410
7829382212178,22sleep40-21swapper/419:05:144
7830302210184,16sleep20-21swapper/219:06:332
7829912210156,18sleep10-21swapper/119:05:591
78544499374,3cyclictest0-21swapper/320:50:023
78545399330,1cyclictest278-21plymouthd00:10:026
785453993228,4cyclictest771ktimers/619:33:056
78545399320,31cyclictest0-21swapper/600:13:056
785455993128,2cyclictest0-21swapper/700:30:027
78545399310,27cyclictest0-21swapper/621:00:026
78545099310,30cyclictest812902-21sh20:00:015
785455993027,2cyclictest842514-21sh20:55:027
78545599300,1cyclictest0-21swapper/721:25:017
785450993028,1cyclictest916671-21apt-get23:13:045
785450993026,3cyclictest932446-21sh23:40:015
78545099300,29cyclictest0-21swapper/520:50:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional