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2026-04-24 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Fri Apr 24, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21922042258186,23sleep40-21swapper/419:08:494
21899252240174,22sleep60-21swapper/619:05:056
21921272231170,20sleep10-21swapper/119:07:411
21922212221186,21sleep30-21swapper/319:09:043
21920562221188,21sleep70-21swapper/719:06:437
21920312213182,20sleep20-21swapper/219:06:222
21919892213186,17sleep50-21swapper/519:05:445
21919732209176,21sleep00-21swapper/019:05:310
2192500993431,2cyclictest100-21kauditd23:45:012
2192502993328,4cyclictest2229314-21unix_chkpwd20:15:013
219249499332,3cyclictest18-1pr/ttyS000:25:010
219251299320,31cyclictest2209806-21cron19:40:007
219251299320,1cyclictest2206980-21919:34:357
2192508993227,5cyclictest2304663-21cron22:30:016
219250899320,28cyclictest0-21swapper/622:17:016
219250899320,28cyclictest0-21swapper/622:17:016
2192506993230,2cyclictest2354856-21cmp00:00:015
2192506993230,2cyclictest2354856-21cmp00:00:015
219250299323,28cyclictest18-1pr/ttyS019:55:013
2192494993227,4cyclictest2365774-40systemctl00:17:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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