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2026-02-06 - 02:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Thu Feb 05, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41235712229171,20sleep10-21swapper/119:09:061
41235792227170,19sleep00-21swapper/019:09:140
41236202215186,18sleep20-21swapper/219:09:472
41214322211181,19sleep70-21swapper/719:06:167
41236212210180,19sleep30-21swapper/319:09:483
41214402210181,18sleep60-21swapper/619:06:236
41214392210179,19sleep50-21swapper/519:06:225
41214382207174,21sleep40-21swapper/419:06:214
41336152540,0sleep60-21swapper/619:28:096
4123864994645,0cyclictest0-21swapper/200:33:102
4123868993937,1cyclictest0-21swapper/321:10:013
4123879993333,0cyclictest0-21swapper/721:10:017
412386899320,31cyclictest90416-21apt00:05:013
412387699310,30cyclictest87706-21apt00:00:016
412387699310,30cyclictest6409-21cron21:30:026
412387499310,30cyclictest60800-21idleruntime-cro23:10:005
412386999310,30cyclictest4165073-21apt20:25:014
412387999300,2cyclictest93100-21latency_hist00:10:007
412387999300,29cyclictest90413-21latency_hist00:05:007
412387699300,29cyclictest4129800-21dump-pmu-power19:20:006
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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