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2026-03-04 - 14:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Wed Mar 04, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
660132236183,17sleep60-21swapper/619:08:406
638382232179,17sleep20-21swapper/219:05:142
660292223176,18sleep40-21swapper/419:08:534
638282221192,19sleep10-21swapper/119:05:051
661022217166,40sleep00-21swapper/019:09:540
639082214183,19sleep70-21swapper/719:06:167
640262204176,18sleep30-21swapper/319:07:553
660302203172,19sleep50-21swapper/519:08:555
66348996417,23cyclictest0-21swapper/021:52:270
6636999330,28cyclictest0-21swapper/700:10:017
6636099330,28cyclictest156330-21awk21:55:014
6636099330,28cyclictest124316-21apt-get20:58:034
6636099320,4cyclictest0-21swapper/419:23:054
6635899320,31cyclictest188604-21idleruntime-cro22:55:013
6635299320,0cyclictest0-21swapper/120:58:031
6636999310,30cyclictest172463-21idleruntime-cro22:25:027
66365993127,3cyclictest80352-21sh19:35:016
6635399310,30cyclictest156300-21idleruntime-cro21:55:022
6634899311,29cyclictest107284-21apt20:25:010
6634899310,3cyclictest150917-21awk21:45:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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