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2026-05-07 - 05:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Thu May 07, 2026 00:44:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40715592231168,19sleep40-21swapper/419:07:474
40715132225166,48sleep30-21swapper/319:07:063
40714642218188,20sleep10-21swapper/119:06:231
40715822214184,20sleep70-21swapper/719:08:057
40715572213185,18sleep20-21swapper/219:07:452
40715072212184,18sleep60-21swapper/619:07:016
40714122212152,18sleep50-21swapper/519:05:395
40716672206177,20sleep00-21swapper/019:09:190
414340821410,0sleep60-21swapper/621:15:186
407193899401,38cyclictest0-21swapper/519:40:155
4071946993432,1cyclictest17850irq/4-ttyS022:05:017
4071938993430,3cyclictest34746-21sh23:50:015
407192799340,1cyclictest0-21swapper/120:35:151
407192799340,1cyclictest0-21swapper/120:35:021
407192799330,1cyclictest0-21swapper/121:30:131
4071925993328,4cyclictest4175725-21cron22:15:010
407194699322,29cyclictest17850irq/4-ttyS022:35:017
407194299321,30cyclictest856-21dbus-daemon21:00:006
407193399320,31cyclictest1-21systemd20:10:023
407192799320,31cyclictest0-21swapper/123:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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