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2026-08-23 - 01:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Sat Aug 22, 2026 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31789482239172,21sleep60-21swapper/607:05:396
31789922229171,47sleep00-21swapper/007:06:120
31789542229166,20sleep30-21swapper/307:05:443
31789882214185,19sleep50-21swapper/507:06:105
31812702213184,19sleep10-21swapper/107:10:001
31789642211180,20sleep40-21swapper/407:05:534
31810522209178,20sleep70-21swapper/707:06:537
31789262204175,19sleep20-21swapper/207:05:192
318149399360,31cyclictest3343758-21cron12:00:027
3181493993330,3cyclictest17950irq/4-ttyS012:10:027
3181482993329,4cyclictest3360841-21latency_hist12:30:023
3181482993326,6cyclictest3343745-21cron12:00:023
318148299330,32cyclictest0-21swapper/312:35:023
318148899320,31cyclictest3299211-21cron10:40:016
318148899320,31cyclictest1-21systemd11:40:016
3181482993227,4cyclictest3221183-21cron08:20:023
318148299320,28cyclictest289-21plymouthd12:15:013
318147899320,31cyclictest3352162-21912:15:022
318149399312,29cyclictest17950irq/4-ttyS007:30:017
318149399310,3cyclictest3229527-21cron08:35:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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