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2026-02-20 - 09:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Fri Feb 20, 2026 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7715222234178,17sleep60-21swapper/619:05:066
7717182230173,18sleep40-21swapper/419:07:534
7715772229172,19sleep30-21swapper/319:05:523
7717252227172,17sleep20-21swapper/219:08:002
7737152226191,23sleep70-21swapper/719:08:457
7717282222172,39sleep50-21swapper/519:08:025
7716872221167,42sleep10-21swapper/119:07:271
7737352214185,19sleep00-21swapper/019:09:020
77404299322,28cyclictest0-21swapper/422:40:014
77404299322,28cyclictest0-21swapper/422:40:004
77403999320,3cyclictest823647-21apt-key20:40:013
77405099310,30cyclictest907861-21idleruntime-cro23:15:017
77404299310,30cyclictest840013-21turbostat.cron21:10:014
77404299310,29cyclictest776602-21turbostat.cron19:15:014
77404899300,2cyclictest807431-21turbostat20:10:016
77404899300,29cyclictest793722-21munin-run19:45:026
774044993028,1cyclictest0-21swapper/521:50:015
77404499300,29cyclictest858870-21sh21:45:015
774042993027,2cyclictest818203-21idleruntime-cro20:30:004
77404299300,29cyclictest0-21swapper/423:35:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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