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2026-03-10 - 15:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4.osadl.org (updated Tue Mar 10, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17290262244186,18sleep40-21swapper/407:09:394
17289852220185,22sleep20-21swapper/207:09:042
17269632220166,18sleep00-21swapper/007:07:500
17268162220168,17sleep50-21swapper/507:05:455
17268092220189,20sleep70-21swapper/707:05:407
17289972216189,17sleep30-21swapper/307:09:133
17268802213183,19sleep10-21swapper/107:06:381
17269502204174,20sleep60-21swapper/607:07:396
1729270993529,5cyclictest1-21systemd08:05:021
172927099350,1cyclictest1-21systemd12:20:021
172927599344,29cyclictest698-21in:imuxsock09:45:012
172929299330,32cyclictest0-21swapper/708:30:017
1729270993326,2cyclictest369-21systemd-journal08:00:021
172927099330,28cyclictest0-21swapper/109:38:031
172927099330,1cyclictest1743559-21latency_hist07:35:021
1729270993227,0cyclictest0-21swapper/111:50:021
1729292993128,2cyclictest16450irq/4-ttyS011:20:027
172928399310,3cyclictest1767799-21cron08:20:014
172928199310,29cyclictest1814373-21sh09:45:013
1729275993129,1cyclictest0-21swapper/212:15:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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