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2026-02-08 - 21:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot4s.osadl.org (updated Sun Feb 08, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12437782240175,22sleep10-21swapper/107:09:051
12437932222192,19sleep30-21swapper/307:09:153
12436242213184,18sleep40-21swapper/407:06:514
12435432213176,24sleep60-21swapper/607:05:416
12437392210177,21sleep70-21swapper/707:08:317
12438372209176,21sleep00-21swapper/007:09:530
12437792209175,21sleep20-21swapper/207:09:052
12436342203175,18sleep50-21swapper/507:07:005
1244088992825,2cyclictest1262015-21fwupd07:39:177
1244077992725,1cyclictest1262015-21fwupd07:39:173
1244088992623,2cyclictest1435146-21tr12:40:007
124408899258,0cyclictest0-21swapper/711:54:577
124407399250,24cyclictest0-21swapper/212:25:142
124406599250,25cyclictest0-21swapper/007:14:590
124408899240,23cyclictest0-21swapper/712:10:127
124408899240,23cyclictest0-21swapper/709:30:107
1244084992420,3cyclictest1310698-21perf09:05:006
1244082992422,1cyclictest0-21swapper/510:00:015
124408299240,23cyclictest0-21swapper/512:20:115
124408299240,1cyclictest0-21swapper/512:15:005
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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