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2026-10-20 - 01:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Mon Oct 19, 2026 12:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6586
"cycles":100000000,6585
"load":"idle",6584
"condition":{6583
"clock":"3400"6581
"family":"x86",6580
"vendor":"Intel",6579
"processor":{6577
"dataset":"2024-01-08T15:37:47+0100"6575
"origin":"2024-01-08T12:43:21+0100",6574
"timestamps":{6573
"granularity":"microseconds"6571
2017:23:086569
18,17:23:066568
18,17:23:066567
19,17:23:076566
18,17:23:066565
18,17:23:066564
18,17:23:066563
18,17:23:066562
"maxima":[6561
017:22:486558
0,17:22:486557
0,17:22:486556
0,17:22:486555
0,17:22:486554
0,17:22:486553
0,17:22:486552
0,17:22:486551
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0,17:22:486549
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0,17:22:486546
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0,17:22:486542
0,17:22:486541
0,17:22:486540
0,17:22:486539
0,17:22:486538
0,17:22:486537
0,17:22:486536
0,17:22:486535
0,17:22:486534
0,17:22:486533
0,17:22:486532
0,17:22:486531
0,17:22:486530
0,17:22:486529
0,17:22:486528
0,17:22:486527
0,17:22:486526
0,17:22:486525
0,17:22:486524
0,17:22:486523
0,17:22:486522
0,17:22:486521
0,17:22:486520
0,17:22:486519
0,17:22:486518
0,17:22:486517
0,17:22:486516
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0,17:22:486514
0,17:22:486513
0,17:22:486512
0,17:22:486511
0,17:22:486510
0,17:22:486509
0,17:22:486508
0,17:22:486507
0,17:22:486506
0,17:22:486505
0,17:22:486504
0,17:22:486503
0,17:22:486502
0,17:22:486501
0,17:22:486500
0,17:22:486499
0,17:22:486498
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0,17:22:486480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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