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2023-10-04 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack8slot5.osadl.org (updated Wed Oct 04, 2023 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123025928,8sleep40-21swapper/417:09:494
136725827,8sleep70-21swapper/717:11:447
123825332,8sleep30-21swapper/317:09:563
133225029,8sleep10-21swapper/117:11:141
108025029,8sleep50-21swapper/517:07:425
128524928,8sleep20-21swapper/217:10:352
109924929,8sleep60-21swapper/617:07:596
114124726,7sleep00-21swapper/017:08:330
151799169,1cyclictest8802-21sa120:21:464
151799160,15cyclictest0-21swapper/419:38:154
1502991512,2cyclictest0-21swapper/019:47:100
152799140,13cyclictest0-21swapper/720:27:117
152699140,13cyclictest0-21swapper/619:54:286
152699140,13cyclictest0-21swapper/619:37:126
152599140,13cyclictest0-21swapper/519:54:115
151799140,9cyclictest0-21swapper/419:54:504
150899140,13cyclictest0-21swapper/219:23:542
150299140,13cyclictest0-21swapper/019:53:150
150299140,13cyclictest0-21swapper/019:39:380
152799130,6cyclictest0-21swapper/722:38:127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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