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2025-07-01 - 05:20

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Tue Jul 01, 2025 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27362993434,0cyclictest5787-21fwupd00:28:180
27362991918,1cyclictest66850irq/125-lan23:25:160
27362991918,1cyclictest66850irq/125-lan23:01:410
27362991918,1cyclictest66850irq/125-lan21:48:200
27362991918,1cyclictest66850irq/125-lan19:13:330
27371991818,0cyclictest771-21snmpd23:39:042
27371991818,0cyclictest771-21snmpd23:21:062
27371991818,0cyclictest771-21snmpd22:13:072
27371991818,0cyclictest771-21snmpd21:25:422
27371991818,0cyclictest771-21snmpd19:27:382
27371991818,0cyclictest30562-21cat00:20:172
27371991818,0cyclictest15377-21cat22:55:182
27362991818,0cyclictest66850irq/125-lan22:34:450
27362991818,0cyclictest66850irq/125-lan21:30:200
27362991818,0cyclictest66850irq/125-lan21:26:190
27362991818,0cyclictest66850irq/125-lan21:20:200
27362991818,0cyclictest66850irq/125-lan21:15:160
27362991818,0cyclictest66850irq/125-lan20:20:330
27362991817,1cyclictest66850irq/125-lan23:54:420
27362991817,1cyclictest66850irq/125-lan23:40:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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