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2026-02-25 - 11:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Wed Feb 25, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30947991918,1cyclictest65850irq/126-lan22:25:172
30947991818,0cyclictest743-21snmpd23:36:462
30947991818,0cyclictest65850irq/126-lan22:22:322
30947991818,0cyclictest65850irq/126-lan20:10:212
30947991818,0cyclictest65850irq/126-lan19:30:122
30947991817,1cyclictest65850irq/126-lan23:15:182
30947991717,0cyclictest9680-21cat19:35:142
30947991717,0cyclictest743-21snmpd19:25:172
30947991717,0cyclictest743-21snmpd00:15:222
30947991717,0cyclictest65850irq/126-lan23:55:162
30947991717,0cyclictest65850irq/126-lan22:10:062
30947991717,0cyclictest65850irq/126-lan21:10:492
30947991717,0cyclictest65850irq/126-lan20:40:152
30947991717,0cyclictest65850irq/126-lan00:10:202
30947991717,0cyclictest14045-21cat21:05:142
30947991716,1cyclictest65850irq/126-lan21:00:142
30947991616,0cyclictest743-21snmpd23:05:212
30947991616,0cyclictest743-21snmpd21:28:152
30947991616,0cyclictest65850irq/126-lan23:50:162
30947991616,0cyclictest65850irq/126-lan23:43:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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