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2026-09-17 - 00:02

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Wed Sep 16, 2026 12:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174409910511050,1cyclictest9042-21kworker/3:0+events09:25:233
174409910511048,2cyclictest2913-21kworker/3:1+events11:45:213
174319910501049,1cyclictest8961-21kworker/1:2+events08:11:511
174259910501047,2cyclictest19813-21kworker/0:0+events10:13:170
174259910481046,2cyclictest13223-21kworker/0:1+events11:20:330
174409910471046,1cyclictest13853-21kworker/3:2+events09:38:153
174319910461043,2cyclictest19635-21kworker/1:1+events12:37:321
174259910461045,1cyclictest27080-21kworker/0:1+events07:36:150
174319910441043,1cyclictest5006-21kworker/1:0+events12:15:451
174319910431040,3cyclictest10172-21turbostat09:59:541
174409910351034,1cyclictest13259-21kworker/3:0+events08:26:053
174409910341033,1cyclictest2913-21kworker/3:1+events11:42:173
174389910311029,2cyclictest2378-21turbostat09:14:552
174319910281026,2cyclictest27170-21kworker/1:1+events12:08:081
174389910271024,3cyclictest4746-21turbostat10:29:552
174319910261024,2cyclictest19335-21kworker/1:1+events07:18:361
174409910251024,1cyclictest13853-21kworker/3:2+events09:43:163
174409910231021,2cyclictest12890-21turbostat11:14:563
174259910221021,1cyclictest27080-21kworker/0:1+events08:49:470
174319910191015,4cyclictest26563-21turbostat11:29:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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