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2026-02-21 - 06:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Sat Feb 21, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12415992019,1cyclictest65850irq/126-lan20:35:202
12410991919,0cyclictest743-21snmpd23:44:411
12415991817,1cyclictest65850irq/126-lan22:10:202
12415991817,1cyclictest65850irq/126-lan22:10:192
12415991817,1cyclictest65850irq/126-lan22:00:182
12415991817,1cyclictest65850irq/126-lan21:35:162
12415991817,1cyclictest65850irq/126-lan20:15:152
12410991818,0cyclictest743-21snmpd23:14:191
12410991818,0cyclictest743-21snmpd21:31:561
12410991818,0cyclictest743-21snmpd21:10:391
12410991818,0cyclictest743-21snmpd00:35:161
12410991818,0cyclictest15388-21cat20:35:131
12415991717,0cyclictest65850irq/126-lan20:20:122
12415991716,1cyclictest65850irq/126-lan23:50:162
12415991716,1cyclictest65850irq/126-lan21:25:192
12415991716,1cyclictest65850irq/126-lan20:50:162
12415991716,1cyclictest65850irq/126-lan20:05:172
12415991716,1cyclictest65850irq/126-lan19:25:482
12415991715,1cyclictest65850irq/126-lan21:21:062
12410991717,0cyclictest743-21snmpd00:08:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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