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2026-02-16 - 14:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Mon Feb 16, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9302992323,0cyclictest2959-21fwupd12:05:321
9306991918,1cyclictest65850irq/126-lan07:25:122
9306991817,1cyclictest65850irq/126-lan12:35:222
9306991817,1cyclictest65850irq/126-lan12:25:112
9306991817,1cyclictest65850irq/126-lan12:05:142
9306991817,1cyclictest65850irq/126-lan11:50:162
9306991817,1cyclictest65850irq/126-lan11:20:202
9306991817,1cyclictest65850irq/126-lan11:00:192
9306991817,1cyclictest65850irq/126-lan09:15:132
9306991817,1cyclictest65850irq/126-lan09:05:152
9306991817,1cyclictest65850irq/126-lan08:30:112
9306991817,1cyclictest65850irq/126-lan07:55:002
9306991817,1cyclictest65850irq/126-lan07:45:192
9306991817,1cyclictest65850irq/126-lan07:10:212
9302991818,0cyclictest743-21snmpd12:22:001
9302991818,0cyclictest743-21snmpd11:16:241
9302991818,0cyclictest743-21snmpd11:03:181
9302991818,0cyclictest743-21snmpd09:06:141
9302991818,0cyclictest743-21snmpd08:05:031
9306991717,0cyclictest65850irq/126-lan11:32:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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