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2026-01-11 - 03:24

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Sun Jan 11, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2140993535,0cyclictest16844-21fwupd22:24:412
2131991918,1cyclictest65850irq/126-lan22:15:180
2131991918,1cyclictest65850irq/126-lan20:35:110
2131991818,0cyclictest743-21snmpd00:19:080
2131991818,0cyclictest65850irq/126-lan23:59:580
2131991818,0cyclictest65850irq/126-lan23:00:120
2131991818,0cyclictest65850irq/126-lan22:26:020
2131991818,0cyclictest65850irq/126-lan20:55:190
2131991818,0cyclictest65850irq/126-lan20:30:210
2131991817,1cyclictest65850irq/126-lan21:57:180
2131991817,1cyclictest65850irq/126-lan21:57:180
2131991717,0cyclictest65850irq/126-lan23:18:340
2131991717,0cyclictest65850irq/126-lan23:10:120
2131991717,0cyclictest65850irq/126-lan22:00:220
2131991717,0cyclictest65850irq/126-lan21:21:210
2131991717,0cyclictest65850irq/126-lan20:26:060
2131991717,0cyclictest65850irq/126-lan19:40:120
2131991716,1cyclictest65850irq/126-lan23:05:130
2131991716,1cyclictest65850irq/126-lan22:45:140
2131991716,1cyclictest65850irq/126-lan22:30:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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