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2026-01-26 - 10:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Mon Jan 26, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3052991918,1cyclictest65850irq/126-lan19:45:170
3061991817,1cyclictest30318-21cat20:15:132
3052991818,0cyclictest65850irq/126-lan20:38:390
3052991818,0cyclictest65850irq/126-lan20:17:250
3052991817,1cyclictest65850irq/126-lan21:35:180
3052991817,1cyclictest65850irq/126-lan21:30:190
3052991817,1cyclictest65850irq/126-lan21:20:200
3052991817,1cyclictest65850irq/126-lan19:10:160
3052991717,0cyclictest65850irq/126-lan22:20:130
3052991717,0cyclictest65850irq/126-lan21:51:270
3052991716,1cyclictest65850irq/126-lan23:15:180
3052991716,1cyclictest65850irq/126-lan22:45:210
3052991716,1cyclictest65850irq/126-lan22:43:290
3052991716,1cyclictest65850irq/126-lan22:30:210
3052991716,1cyclictest65850irq/126-lan21:55:130
3052991716,1cyclictest65850irq/126-lan21:11:550
3052991716,1cyclictest65850irq/126-lan19:55:130
3052991716,1cyclictest65850irq/126-lan00:15:150
3052991716,1cyclictest65850irq/126-lan00:10:140
3052991716,0cyclictest65850irq/126-lan21:25:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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