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2025-08-30 - 00:46

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Fri Aug 29, 2025 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17300991918,1cyclictest66850irq/125-lan12:40:000
17300991918,1cyclictest66850irq/125-lan11:56:090
17300991918,1cyclictest66850irq/125-lan09:59:440
17300991818,0cyclictest66850irq/125-lan12:14:030
17300991818,0cyclictest66850irq/125-lan11:45:300
17300991818,0cyclictest66850irq/125-lan11:33:170
17300991818,0cyclictest66850irq/125-lan11:16:310
17300991818,0cyclictest66850irq/125-lan11:10:130
17300991818,0cyclictest66850irq/125-lan10:53:510
17300991818,0cyclictest66850irq/125-lan09:50:520
17300991818,0cyclictest66850irq/125-lan09:16:450
17300991817,1cyclictest66850irq/125-lan12:27:590
17300991817,1cyclictest66850irq/125-lan12:09:120
17300991817,1cyclictest66850irq/125-lan12:00:140
17300991817,1cyclictest66850irq/125-lan11:40:070
17300991817,1cyclictest66850irq/125-lan11:20:500
17300991817,1cyclictest66850irq/125-lan10:55:370
17300991817,1cyclictest66850irq/125-lan10:55:360
17300991817,1cyclictest66850irq/125-lan10:25:170
17300991817,1cyclictest66850irq/125-lan10:07:410
17300991817,1cyclictest66850irq/125-lan09:35:140
17300991817,1cyclictest66850irq/125-lan07:35:150
17300991717,0cyclictest66850irq/125-lan11:29:240
17300991717,0cyclictest66850irq/125-lan11:05:100
17300991717,0cyclictest66850irq/125-lan10:36:340
17300991717,0cyclictest66850irq/125-lan10:23:250
17300991717,0cyclictest66850irq/125-lan10:16:080
17300991717,0cyclictest66850irq/125-lan10:13:150
17300991717,0cyclictest66850irq/125-lan10:02:300
17300991717,0cyclictest66850irq/125-lan09:06:500
17300991716,1cyclictest66850irq/125-lan12:30:450
17300991716,1cyclictest66850irq/125-lan12:24:240
17300991716,1cyclictest66850irq/125-lan12:18:510
17300991716,1cyclictest66850irq/125-lan11:52:320
17300991716,1cyclictest66850irq/125-lan11:03:180
17300991716,1cyclictest66850irq/125-lan11:03:170
17300991716,1cyclictest66850irq/125-lan10:45:160
17300991716,1cyclictest66850irq/125-lan10:30:180
17300991716,1cyclictest66850irq/125-lan09:41:090
17300991716,1cyclictest66850irq/125-lan09:28:540
17300991616,0cyclictest66850irq/125-lan10:43:150
17300991616,0cyclictest66850irq/125-lan09:46:000
17300991616,0cyclictest66850irq/125-lan09:10:180
17300991616,0cyclictest66850irq/125-lan08:59:410
17300991616,0cyclictest66850irq/125-lan08:35:160
17300991616,0cyclictest66850irq/125-lan08:32:400
17300991616,0cyclictest66850irq/125-lan08:00:180
17300991616,0cyclictest66850irq/125-lan07:40:150
17300991616,0cyclictest66850irq/125-lan07:15:150
17300991615,1cyclictest66850irq/125-lan11:36:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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