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2026-08-31 - 20:23

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Mon Aug 31, 2026 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127349910531050,3cyclictest19577-21kworker/1:1+events11:16:291
127349910531050,2cyclictest26651-21kworker/1:2+events11:01:501
127349910531049,2cyclictest30056-21kworker/1:2+events12:21:291
127349910531049,2cyclictest20298-21kworker/1:0+events11:26:171
127439910521050,2cyclictest3693-21kworker/3:2+events08:16:373
127439910521049,3cyclictest7895-21kworker/3:2+events10:45:453
127349910521049,2cyclictest19577-21kworker/1:1+events11:05:231
127439910511049,2cyclictest22483-21kworker/3:0+events12:30:463
127349910511048,2cyclictest20298-21kworker/1:0+events11:24:451
127439910501049,1cyclictest29571-21kworker/3:2+events09:46:383
127349910501048,2cyclictest26651-21kworker/1:2+events10:15:441
127439910491048,1cyclictest24685-21kworker/3:0+events09:41:073
127349910481046,2cyclictest8318-21kworker/1:0+events12:15:441
127349910481046,2cyclictest26651-21kworker/1:2+events11:12:551
127439910471044,3cyclictest17760-21kworker/3:2+events09:10:433
127439910391036,3cyclictest17760-21kworker/3:2+events09:20:213
127439910341031,3cyclictest17760-21kworker/3:2+events09:27:583
127439910311029,2cyclictest17760-21kworker/3:2+events09:05:223
127439910291027,2cyclictest7895-21kworker/3:2+events10:56:153
127439910291027,2cyclictest19961-21turbostat08:49:563
127439910291026,3cyclictest25983-21kworker/3:1+events10:40:443
127439910281025,3cyclictest25983-21kworker/3:1+events10:33:493
127439910281025,3cyclictest17760-21kworker/3:2+events09:31:063
127439910251022,3cyclictest7895-21kworker/3:2+events12:28:213
127439910251022,3cyclictest18603-21kworker/3:1+events08:06:083
127399910241022,2cyclictest10335-21kworker/2:1+events11:45:422
127319910231022,1cyclictest511-21kworker/0:2+events09:58:410
127319910231022,1cyclictest23570-21kworker/0:0+events10:25:410
127439910221020,2cyclictest12379-21kworker/3:2+events07:12:363
127439910211019,2cyclictest7895-21kworker/3:2+events10:38:463
127439910211019,2cyclictest11601-21kworker/3:0+events08:22:123
127399910211020,1cyclictest10335-21kworker/2:1+events11:44:552
127319910211020,1cyclictest18683-21kworker/0:1+events10:13:040
127439910201017,3cyclictest7895-21kworker/3:2+events10:54:053
127439910201016,4cyclictest25688-21turbostat10:19:553
127439910191017,2cyclictest10331-21kworker/3:0+events07:19:143
127439910191016,3cyclictest18603-21kworker/3:1+events08:11:053
127439910181016,2cyclictest17163-21kworker/3:1+events12:39:273
127319910171016,1cyclictest31089-21kworker/0:2+events10:22:120
127439910161014,2cyclictest17760-21kworker/3:2+events09:04:323
127439910161013,3cyclictest25983-21kworker/3:1+events09:39:443
127439910161013,3cyclictest11850-21turbostat10:04:553
127439910141011,3cyclictest10331-21kworker/3:0+events07:20:233
127439910131011,2cyclictest3374-21turbostat12:14:553
127439910131010,3cyclictest18603-21kworker/3:1+events08:03:513
127439910121009,3cyclictest11601-21kworker/3:0+events08:25:543
127439910081006,2cyclictest17760-21kworker/3:2+events09:17:183
127439910081006,2cyclictest13662-21kworker/3:1+events08:32:543
127319910051004,1cyclictest511-21kworker/0:2+events09:50:210
127439910031001,2cyclictest11601-21kworker/3:0+events08:38:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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