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2026-01-09 - 09:41

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Fri Jan 09, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5469993434,0cyclictest32707-21fwupd21:33:422
5469993434,0cyclictest32707-21fwupd21:33:412
5461991918,1cyclictest65850irq/126-lan00:25:160
5461991818,0cyclictest65850irq/126-lan22:50:200
5461991818,0cyclictest65850irq/126-lan00:35:110
5461991817,1cyclictest65850irq/126-lan23:20:000
5461991817,1cyclictest65850irq/126-lan23:00:160
5461991817,1cyclictest65850irq/126-lan21:26:020
5461991717,0cyclictest743-21snmpd20:17:310
5461991717,0cyclictest65850irq/126-lan23:25:140
5461991717,0cyclictest65850irq/126-lan22:00:150
5461991717,0cyclictest65850irq/126-lan20:55:270
5461991716,1cyclictest65850irq/126-lan23:45:130
5461991716,1cyclictest65850irq/126-lan23:42:380
5461991716,1cyclictest65850irq/126-lan22:20:100
5461991716,1cyclictest65850irq/126-lan19:35:120
5461991716,1cyclictest65850irq/126-lan19:15:130
5464991616,0cyclictest7222-21cat21:50:141
5461991616,0cyclictest743-21snmpd22:48:190
5461991616,0cyclictest743-21snmpd21:43:580
5461991616,0cyclictest743-21snmpd20:10:340
5461991616,0cyclictest65850irq/126-lan23:35:110
5461991616,0cyclictest65850irq/126-lan22:05:460
5461991616,0cyclictest65850irq/126-lan21:55:160
5461991616,0cyclictest65850irq/126-lan21:55:000
5461991616,0cyclictest65850irq/126-lan21:20:180
5461991616,0cyclictest65850irq/126-lan19:40:140
5461991616,0cyclictest65850irq/126-lan00:30:180
5461991616,0cyclictest65850irq/126-lan00:18:010
5461991616,0cyclictest5183-21cat21:45:140
5461991615,1cyclictest65850irq/126-lan23:20:150
5461991615,1cyclictest65850irq/126-lan22:35:590
5461991615,1cyclictest65850irq/126-lan22:25:210
5461991615,1cyclictest65850irq/126-lan21:05:180
5461991615,1cyclictest65850irq/126-lan21:00:160
5461991615,1cyclictest65850irq/126-lan19:10:140
5461991615,1cyclictest65850irq/126-lan00:10:190
5461991615,1cyclictest65850irq/126-lan00:10:000
5461991515,0cyclictest743-21snmpd22:12:350
5461991515,0cyclictest743-21snmpd19:33:480
5461991515,0cyclictest743-21snmpd19:27:030
5461991515,0cyclictest65850irq/126-lan23:32:150
5461991515,0cyclictest65850irq/126-lan23:05:150
5461991515,0cyclictest65850irq/126-lan21:30:110
5461991515,0cyclictest65850irq/126-lan21:30:110
5461991515,0cyclictest65850irq/126-lan20:52:450
5461991515,0cyclictest65850irq/126-lan20:30:240
5461991515,0cyclictest65850irq/126-lan20:25:130
5461991515,0cyclictest65850irq/126-lan19:55:160
5461991515,0cyclictest65850irq/126-lan19:24:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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