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2025-12-26 - 15:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Fri Dec 26, 2025 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25504992222,0cyclictest440-21hwrng10:41:430
25504992121,0cyclictest440-21hwrng11:39:050
25504992121,0cyclictest440-21hwrng07:16:560
25504992020,0cyclictest440-21hwrng12:20:020
25504991919,0cyclictest440-21hwrng10:56:030
25504991918,1cyclictest65850irq/126-lan10:15:140
25504991818,0cyclictest65850irq/126-lan08:52:040
25504991817,1cyclictest65850irq/126-lan11:51:080
25504991817,1cyclictest65850irq/126-lan11:45:120
25504991717,0cyclictest743-21snmpd10:24:440
25504991717,0cyclictest743-21snmpd09:42:180
25504991717,0cyclictest65850irq/126-lan12:33:190
25504991717,0cyclictest65850irq/126-lan12:30:000
25504991717,0cyclictest65850irq/126-lan10:10:170
25504991717,0cyclictest65850irq/126-lan09:25:110
25504991717,0cyclictest65850irq/126-lan08:25:180
25504991717,0cyclictest65850irq/126-lan07:45:130
25504991716,1cyclictest65850irq/126-lan12:05:130
25504991716,1cyclictest65850irq/126-lan07:35:150
25504991616,0cyclictest743-21snmpd11:24:010
25504991616,0cyclictest743-21snmpd09:00:050
25504991616,0cyclictest743-21snmpd07:53:160
25504991616,0cyclictest65850irq/126-lan11:29:200
25504991616,0cyclictest65850irq/126-lan11:15:220
25504991616,0cyclictest65850irq/126-lan10:05:120
25504991616,0cyclictest65850irq/126-lan09:20:100
25504991616,0cyclictest65850irq/126-lan08:41:210
25504991616,0cyclictest65850irq/126-lan07:40:140
25504991615,1cyclictest65850irq/126-lan12:00:220
25504991615,1cyclictest65850irq/126-lan09:45:140
25504991615,1cyclictest65850irq/126-lan09:30:190
25515991515,0cyclictest440-21hwrng12:32:193
25515991515,0cyclictest440-21hwrng12:21:043
25515991515,0cyclictest440-21hwrng12:15:573
25515991515,0cyclictest440-21hwrng12:01:373
25515991515,0cyclictest440-21hwrng11:58:313
25515991515,0cyclictest440-21hwrng11:47:163
25515991515,0cyclictest440-21hwrng11:40:063
25515991515,0cyclictest440-21hwrng11:17:353
25515991515,0cyclictest440-21hwrng11:12:263
25515991515,0cyclictest440-21hwrng11:07:203
25515991515,0cyclictest440-21hwrng11:02:133
25515991515,0cyclictest440-21hwrng10:54:013
25515991515,0cyclictest440-21hwrng10:44:483
25515991515,0cyclictest440-21hwrng10:38:393
25515991515,0cyclictest440-21hwrng10:33:333
25515991515,0cyclictest440-21hwrng10:26:233
25515991515,0cyclictest440-21hwrng10:03:513
25515991515,0cyclictest440-21hwrng09:52:343
25515991515,0cyclictest440-21hwrng09:38:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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