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2026-02-02 - 12:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Mon Feb 02, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29489991919,0cyclictest65850irq/126-lan00:07:010
29489991818,0cyclictest65850irq/126-lan20:33:200
29489991817,1cyclictest65850irq/126-lan19:40:180
29489991817,1cyclictest65850irq/126-lan00:35:200
29489991717,0cyclictest65850irq/126-lan21:47:060
29489991716,1cyclictest65850irq/126-lan22:30:180
29489991716,1cyclictest65850irq/126-lan21:35:430
29489991716,1cyclictest65850irq/126-lan21:22:180
29489991716,1cyclictest65850irq/126-lan20:50:190
29489991716,1cyclictest65850irq/126-lan20:15:200
29489991716,1cyclictest65850irq/126-lan19:55:140
29489991716,1cyclictest65850irq/126-lan00:30:140
29489991616,0cyclictest65850irq/126-lan22:45:160
29489991616,0cyclictest65850irq/126-lan22:17:200
29489991615,1cyclictest65850irq/126-lan23:55:160
29489991615,1cyclictest65850irq/126-lan23:10:140
29489991615,1cyclictest65850irq/126-lan22:05:210
29489991615,1cyclictest65850irq/126-lan21:25:160
29489991615,1cyclictest65850irq/126-lan21:25:160
29489991615,1cyclictest65850irq/126-lan19:35:130
29489991615,1cyclictest65850irq/126-lan19:25:140
29489991615,1cyclictest65850irq/126-lan19:10:190
29489991515,0cyclictest65850irq/126-lan23:43:240
29489991515,0cyclictest65850irq/126-lan23:37:150
29489991515,0cyclictest65850irq/126-lan23:00:050
29489991515,0cyclictest65850irq/126-lan22:50:180
29489991515,0cyclictest65850irq/126-lan22:35:200
29489991515,0cyclictest65850irq/126-lan21:58:200
29489991515,0cyclictest65850irq/126-lan21:30:120
29489991514,1cyclictest65850irq/126-lan23:05:170
29489991514,1cyclictest65850irq/126-lan21:05:210
29489991514,1cyclictest65850irq/126-lan20:05:200
29489991414,0cyclictest65850irq/126-lan23:50:130
29489991414,0cyclictest65850irq/126-lan21:50:170
29489991414,0cyclictest65850irq/126-lan20:40:130
29489991413,1cyclictest65850irq/126-lan23:15:160
29489991413,1cyclictest65850irq/126-lan21:40:150
29489991413,1cyclictest65850irq/126-lan00:20:140
29489991313,0cyclictest65850irq/126-lan23:45:100
29489991313,0cyclictest65850irq/126-lan22:40:200
29489991313,0cyclictest65850irq/126-lan22:14:200
29489991313,0cyclictest65850irq/126-lan21:15:230
29489991313,0cyclictest65850irq/126-lan20:55:120
29489991313,0cyclictest65850irq/126-lan20:20:140
29489991313,0cyclictest65850irq/126-lan20:00:320
29489991313,0cyclictest65850irq/126-lan19:31:590
29489991313,0cyclictest65850irq/126-lan19:15:110
29489991313,0cyclictest65850irq/126-lan00:25:120
29489991313,0cyclictest65850irq/126-lan00:03:370
29489991312,1cyclictest65850irq/126-lan20:45:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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