You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-19 - 12:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Mon Jan 19, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28698991918,1cyclictest65850irq/126-lan21:10:290
28698991817,1cyclictest65850irq/126-lan23:11:010
28698991817,1cyclictest65850irq/126-lan19:40:140
28698991817,1cyclictest65850irq/126-lan00:20:190
28698991717,0cyclictest65850irq/126-lan22:55:110
28698991717,0cyclictest65850irq/126-lan22:29:290
28698991717,0cyclictest65850irq/126-lan21:50:170
28698991717,0cyclictest65850irq/126-lan21:25:470
28698991717,0cyclictest65850irq/126-lan20:49:220
28698991717,0cyclictest65850irq/126-lan19:11:330
28698991717,0cyclictest65850irq/126-lan00:05:170
28698991716,1cyclictest65850irq/126-lan22:05:010
28698991716,1cyclictest65850irq/126-lan21:15:120
28698991716,1cyclictest65850irq/126-lan20:41:080
28698991716,1cyclictest65850irq/126-lan20:30:260
28698991716,1cyclictest65850irq/126-lan19:15:130
28698991616,0cyclictest65850irq/126-lan22:35:130
28698991616,0cyclictest65850irq/126-lan20:35:150
28698991615,1cyclictest65850irq/126-lan22:40:200
28698991615,1cyclictest65850irq/126-lan21:45:110
28698991615,1cyclictest65850irq/126-lan21:30:130
28698991615,1cyclictest65850irq/126-lan20:25:170
28698991615,1cyclictest65850irq/126-lan20:20:170
28698991615,1cyclictest65850irq/126-lan19:35:120
28698991615,1cyclictest65850irq/126-lan00:00:190
28698991515,0cyclictest65850irq/126-lan21:05:180
28698991515,0cyclictest65850irq/126-lan21:00:150
28698991515,0cyclictest65850irq/126-lan20:50:200
28698991515,0cyclictest65850irq/126-lan20:10:150
28698991515,0cyclictest65850irq/126-lan19:57:320
28698991514,1cyclictest65850irq/126-lan23:55:190
28698991514,1cyclictest65850irq/126-lan19:30:160
28698991514,1cyclictest65850irq/126-lan00:15:140
28710991414,0cyclictest19396-21fwupd22:41:532
28698991414,0cyclictest65850irq/126-lan23:06:080
28698991414,0cyclictest65850irq/126-lan22:50:170
28698991413,1cyclictest65850irq/126-lan23:50:170
28698991413,1cyclictest65850irq/126-lan23:20:120
28698991413,1cyclictest65850irq/126-lan23:00:210
28698991413,1cyclictest65850irq/126-lan22:15:150
28698991413,1cyclictest65850irq/126-lan21:35:170
28698991413,1cyclictest65850irq/126-lan19:25:110
28698991413,1cyclictest65850irq/126-lan00:30:190
28698991313,0cyclictest65850irq/126-lan23:15:130
28698991313,0cyclictest65850irq/126-lan21:20:160
28698991313,0cyclictest65850irq/126-lan19:50:150
28698991312,1cyclictest65850irq/126-lan22:20:140
28698991312,1cyclictest65850irq/126-lan22:10:120
28698991312,1cyclictest65850irq/126-lan20:55:160
28698991212,0cyclictest65850irq/126-lan00:25:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional