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2026-03-04 - 19:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot7.osadl.org (updated Wed Mar 04, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23326991918,1cyclictest59550irq/125-lan07:50:121
23326991818,0cyclictest59550irq/125-lan07:45:321
23326991817,1cyclictest59550irq/125-lan10:55:161
23326991817,1cyclictest59550irq/125-lan10:45:121
23326991817,1cyclictest59550irq/125-lan09:50:001
23326991717,0cyclictest59550irq/125-lan10:20:111
23326991717,0cyclictest59550irq/125-lan09:00:151
23326991716,1cyclictest59550irq/125-lan11:30:131
23326991716,1cyclictest59550irq/125-lan08:35:111
23326991716,1cyclictest59550irq/125-lan08:30:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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