You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-22 - 14:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot7.osadl.org (updated Sun Feb 22, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17977991818,0cyclictest59550irq/125-lan22:58:001
17977991817,1cyclictest59550irq/125-lan22:50:161
17977991817,1cyclictest59550irq/125-lan20:16:021
17977991817,1cyclictest59550irq/125-lan19:45:161
17977991717,0cyclictest59550irq/125-lan22:45:201
17977991716,1cyclictest59550irq/125-lan23:15:171
17977991716,1cyclictest59550irq/125-lan22:40:141
17977991716,1cyclictest59550irq/125-lan21:30:181
17977991716,1cyclictest59550irq/125-lan20:00:171
17977991716,1cyclictest59550irq/125-lan19:15:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional