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2026-01-21 - 08:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack8slot7.osadl.org (updated Wed Jan 21, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6596993535,0cyclictest22541-21fwupd22:27:282
6596991918,1cyclictest59550irq/125-lan22:30:152
6596991918,1cyclictest59550irq/125-lan21:50:212
6596991817,1cyclictest59550irq/125-lan23:40:202
6596991817,1cyclictest59550irq/125-lan23:05:142
6596991817,1cyclictest59550irq/125-lan22:10:202
6596991817,1cyclictest59550irq/125-lan20:55:152
6596991717,0cyclictest59550irq/125-lan23:50:172
6596991716,1cyclictest59550irq/125-lan23:10:062
6596991716,1cyclictest59550irq/125-lan22:35:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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