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2026-01-27 - 23:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack8slot7.osadl.org (updated Tue Jan 27, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13972994343,0cyclictest24283-21fwupd08:54:342
13977991918,1cyclictest59550irq/125-lan11:10:003
13977991918,1cyclictest59550irq/125-lan11:00:113
13977991918,1cyclictest59550irq/125-lan10:30:193
13977991917,2cyclictest59550irq/125-lan10:05:133
13977991817,1cyclictest59550irq/125-lan10:25:133
13977991817,1cyclictest59550irq/125-lan08:50:183
13977991817,1cyclictest59550irq/125-lan07:20:233
13977991816,2cyclictest59550irq/125-lan11:50:203
13977991816,1cyclictest59550irq/125-lan11:10:143
13977991717,0cyclictest59550irq/125-lan10:40:223
13977991717,0cyclictest59550irq/125-lan09:41:093
13977991716,1cyclictest59550irq/125-lan12:00:123
13977991716,1cyclictest59550irq/125-lan09:30:133
13977991716,1cyclictest59550irq/125-lan07:45:153
13977991716,1cyclictest59550irq/125-lan07:35:213
13977991616,0cyclictest59550irq/125-lan11:55:163
13977991616,0cyclictest59550irq/125-lan10:45:143
13977991616,0cyclictest59550irq/125-lan09:28:413
13977991615,1cyclictest59550irq/125-lan12:05:203
13977991615,1cyclictest59550irq/125-lan11:48:233
13977991615,1cyclictest59550irq/125-lan11:40:113
13977991615,1cyclictest59550irq/125-lan09:35:143
13977991615,1cyclictest59550irq/125-lan09:00:153
13977991614,2cyclictest59550irq/125-lan09:05:183
13977991613,3cyclictest59550irq/125-lan09:15:133
13977991515,0cyclictest59550irq/125-lan12:35:153
13977991515,0cyclictest59550irq/125-lan11:20:163
13977991514,1cyclictest59550irq/125-lan11:15:163
13977991514,1cyclictest59550irq/125-lan10:35:143
13977991514,1cyclictest59550irq/125-lan09:10:173
13977991514,1cyclictest59550irq/125-lan08:20:233
13977991514,1cyclictest59550irq/125-lan07:30:123
13977991514,1cyclictest59550irq/125-lan07:15:143
13977991513,2cyclictest59550irq/125-lan10:00:113
13977991513,2cyclictest59550irq/125-lan09:20:203
13977991512,1cyclictest59550irq/125-lan08:55:163
13977991414,0cyclictest59550irq/125-lan12:25:213
13977991414,0cyclictest59550irq/125-lan08:10:203
13977991413,1cyclictest59550irq/125-lan11:30:123
13977991413,1cyclictest59550irq/125-lan10:50:133
13977991413,1cyclictest59550irq/125-lan10:10:133
13977991413,1cyclictest59550irq/125-lan08:35:183
13977991413,1cyclictest59550irq/125-lan08:25:203
13977991413,1cyclictest59550irq/125-lan08:15:203
13977991412,2cyclictest59550irq/125-lan07:10:143
13977991412,1cyclictest59550irq/125-lan12:30:203
13977991412,1cyclictest59550irq/125-lan07:40:163
13977991411,1cyclictest59550irq/125-lan07:50:203
13972991414,0cyclictest325-21hwrng12:33:292
13967991414,0cyclictest325-21hwrng11:31:011
13977991313,0cyclictest59550irq/125-lan12:20:123
13977991313,0cyclictest59550irq/125-lan08:30:153
13977991312,1cyclictest59550irq/125-lan10:55:163
13977991312,1cyclictest59550irq/125-lan09:45:123
13977991312,1cyclictest59550irq/125-lan07:25:123
13977991312,1cyclictest59550irq/125-lan07:25:123
13977991211,1cyclictest59550irq/125-lan10:15:183
13977991211,1cyclictest59550irq/125-lan08:05:133
13977991111,0cyclictest59550irq/125-lan08:40:173
13977991110,1cyclictest59550irq/125-lan11:35:123
13977991110,1cyclictest59550irq/125-lan11:25:123
13977991110,1cyclictest59550irq/125-lan10:00:003
13977991110,1cyclictest59550irq/125-lan08:45:173
13967991111,0cyclictest325-21hwrng11:49:271
13967991111,0cyclictest325-21hwrng08:55:221
13967991111,0cyclictest325-21hwrng08:44:051
13967991111,0cyclictest325-21hwrng08:05:121
13967991111,0cyclictest325-21hwrng08:04:091
13977991010,0cyclictest59550irq/125-lan12:15:183
13977991010,0cyclictest59550irq/125-lan12:11:293
13977991010,0cyclictest59550irq/125-lan10:20:133
13967991010,0cyclictest325-21hwrng12:26:191
13967991010,0cyclictest325-21hwrng11:35:061
13967991010,0cyclictest1471-21cat11:55:141
13961991010,0cyclictest325-21hwrng11:48:260
139779998,1cyclictest59550irq/125-lan07:55:133
139729997,1cyclictest5897-21kworker/2:0+events_freezable_power_10:19:032
139679999,0cyclictest325-21hwrng09:36:201
139679999,0cyclictest23010-21cat07:30:131
139679998,1cyclictest674-21snmpd10:30:081
139779987,1cyclictest296-21systemd-udevd09:52:513
139729988,0cyclictest674-21snmpd11:57:572
139729988,0cyclictest325-21hwrng12:00:432
139729988,0cyclictest325-21hwrng11:40:142
139729988,0cyclictest325-21hwrng11:00:172
139729988,0cyclictest325-21hwrng10:01:552
139729987,1cyclictest674-21snmpd11:06:322
139729987,1cyclictest674-21snmpd07:48:192
139729987,1cyclictest674-21snmpd07:23:092
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_11:35:562
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_09:57:062
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_09:35:082
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_08:40:132
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_07:56:172
139729987,1cyclictest5897-21kworker/2:0+events_freezable_power_07:12:212
139679988,0cyclictest674-21snmpd10:50:091
139679988,0cyclictest674-21snmpd10:41:311
139679988,0cyclictest674-21snmpd09:58:351
139679988,0cyclictest674-21snmpd09:43:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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