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2026-01-22 - 05:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Thu Jan 22, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14161991917,1cyclictest59550irq/125-lan23:50:202
14161991817,1cyclictest59550irq/125-lan19:55:152
14161991717,0cyclictest59550irq/125-lan22:52:302
14161991717,0cyclictest59550irq/125-lan22:30:172
14161991717,0cyclictest59550irq/125-lan20:35:162
14161991717,0cyclictest59550irq/125-lan19:41:292
14161991716,1cyclictest59550irq/125-lan23:20:122
14161991716,1cyclictest59550irq/125-lan20:25:192
14161991616,0cyclictest59550irq/125-lan23:15:122
14161991616,0cyclictest59550irq/125-lan23:11:242
14161991616,0cyclictest59550irq/125-lan22:11:042
14161991616,0cyclictest59550irq/125-lan21:25:002
14161991616,0cyclictest59550irq/125-lan21:21:292
14161991616,0cyclictest59550irq/125-lan21:10:392
14161991616,0cyclictest59550irq/125-lan20:40:142
14161991616,0cyclictest59550irq/125-lan20:30:202
14161991616,0cyclictest59550irq/125-lan20:23:292
14161991616,0cyclictest59550irq/125-lan20:05:112
14161991616,0cyclictest59550irq/125-lan19:25:152
14161991615,1cyclictest59550irq/125-lan22:35:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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