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2026-08-23 - 00:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Aug 22, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11207991918,1cyclictest59550irq/125-lan11:20:170
11207991917,1cyclictest59550irq/125-lan12:40:010
11207991818,0cyclictest59550irq/125-lan12:30:220
11207991818,0cyclictest59550irq/125-lan08:35:280
11207991817,1cyclictest59550irq/125-lan12:25:140
11207991817,1cyclictest59550irq/125-lan11:50:140
11207991817,1cyclictest59550irq/125-lan11:29:460
11207991817,1cyclictest59550irq/125-lan10:05:200
11207991817,1cyclictest59550irq/125-lan09:19:450
11207991817,1cyclictest59550irq/125-lan09:12:230
11207991817,1cyclictest59550irq/125-lan09:00:110
11207991817,1cyclictest59550irq/125-lan08:00:110
11207991717,0cyclictest59550irq/125-lan10:02:060
11207991717,0cyclictest59550irq/125-lan09:50:190
11207991717,0cyclictest59550irq/125-lan09:43:490
11207991717,0cyclictest59550irq/125-lan09:35:150
11207991717,0cyclictest59550irq/125-lan09:20:340
11207991716,1cyclictest59550irq/125-lan10:15:210
11207991716,1cyclictest59550irq/125-lan09:34:270
11207991716,1cyclictest59550irq/125-lan09:26:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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