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2026-07-08 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Wed Jul 08, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32545991817,1cyclictest59550irq/125-lan20:40:000
32545991717,0cyclictest59550irq/125-lan21:45:120
32545991717,0cyclictest59550irq/125-lan20:05:140
32545991717,0cyclictest59550irq/125-lan19:50:140
32545991717,0cyclictest59550irq/125-lan19:21:060
32545991717,0cyclictest59550irq/125-lan00:10:190
32545991616,0cyclictest59550irq/125-lan22:50:140
32545991616,0cyclictest59550irq/125-lan22:20:120
32545991616,0cyclictest59550irq/125-lan22:15:210
32545991616,0cyclictest59550irq/125-lan22:00:170
32545991616,0cyclictest59550irq/125-lan21:15:160
32545991616,0cyclictest59550irq/125-lan20:50:140
32545991616,0cyclictest59550irq/125-lan20:15:130
32545991616,0cyclictest59550irq/125-lan20:00:100
32545991616,0cyclictest59550irq/125-lan00:25:130
32545991616,0cyclictest59550irq/125-lan00:20:110
32545991615,1cyclictest4988-21kworker/0:2+events21:59:340
32545991515,0cyclictest59550irq/125-lan23:56:280
32545991515,0cyclictest59550irq/125-lan22:55:030
32545991515,0cyclictest59550irq/125-lan22:45:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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