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2026-01-17 - 13:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Jan 17, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16929991918,1cyclictest59550irq/125-lan22:30:202
16929991817,1cyclictest59550irq/125-lan21:35:172
16929991717,0cyclictest59550irq/125-lan22:20:202
16929991717,0cyclictest59550irq/125-lan20:10:582
16929991717,0cyclictest59550irq/125-lan19:16:572
16929991716,1cyclictest59550irq/125-lan23:55:182
16929991716,1cyclictest59550irq/125-lan23:30:092
16929991716,1cyclictest59550irq/125-lan23:25:132
16929991716,1cyclictest59550irq/125-lan23:10:112
16929991716,1cyclictest59550irq/125-lan21:59:562
16929991716,1cyclictest59550irq/125-lan20:55:142
16929991716,1cyclictest59550irq/125-lan20:00:182
16929991716,1cyclictest59550irq/125-lan19:40:132
16929991716,1cyclictest59550irq/125-lan19:35:172
16929991616,0cyclictest59550irq/125-lan00:25:172
16929991615,1cyclictest59550irq/125-lan23:23:522
16929991615,1cyclictest59550irq/125-lan22:41:472
16929991615,1cyclictest59550irq/125-lan22:35:122
16929991615,1cyclictest59550irq/125-lan21:10:182
16929991615,1cyclictest59550irq/125-lan20:20:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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