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2026-01-31 - 13:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Jan 31, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30185991918,1cyclictest59550irq/125-lan23:57:393
30185991817,1cyclictest59550irq/125-lan20:00:203
30185991717,0cyclictest59550irq/125-lan23:32:283
30185991717,0cyclictest59550irq/125-lan23:05:133
30185991717,0cyclictest59550irq/125-lan22:40:133
30185991717,0cyclictest59550irq/125-lan21:46:433
30185991717,0cyclictest59550irq/125-lan21:33:553
30185991716,1cyclictest59550irq/125-lan23:25:133
30185991716,1cyclictest59550irq/125-lan23:10:103
30185991716,1cyclictest59550irq/125-lan21:40:173
30185991716,1cyclictest59550irq/125-lan20:30:183
30185991716,1cyclictest59550irq/125-lan19:57:393
30185991616,0cyclictest59550irq/125-lan21:23:323
30185991616,0cyclictest59550irq/125-lan19:50:113
30185991616,0cyclictest59550irq/125-lan19:30:123
30185991616,0cyclictest59550irq/125-lan00:30:093
30185991616,0cyclictest59550irq/125-lan00:05:123
30185991615,1cyclictest59550irq/125-lan23:00:173
30185991615,1cyclictest59550irq/125-lan22:25:143
30185991615,1cyclictest59550irq/125-lan22:05:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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