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2026-07-05 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Jul 04, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29718991918,1cyclictest59550irq/125-lan08:40:170
29718991818,0cyclictest59550irq/125-lan11:40:200
29718991818,0cyclictest59550irq/125-lan10:00:130
29718991817,1cyclictest59550irq/125-lan10:05:120
29718991817,1cyclictest59550irq/125-lan09:20:110
29718991817,1cyclictest59550irq/125-lan07:30:130
29718991716,1cyclictest59550irq/125-lan12:30:000
29718991716,1cyclictest59550irq/125-lan10:35:190
29718991716,1cyclictest59550irq/125-lan10:30:120
29718991716,1cyclictest59550irq/125-lan09:40:160
29718991716,1cyclictest59550irq/125-lan08:55:170
29718991716,1cyclictest59550irq/125-lan08:30:180
29718991616,0cyclictest59550irq/125-lan11:45:150
29718991616,0cyclictest59550irq/125-lan07:48:430
29718991615,1cyclictest59550irq/125-lan12:35:160
29718991615,1cyclictest59550irq/125-lan11:55:170
29718991615,1cyclictest59550irq/125-lan10:55:140
29718991615,1cyclictest59550irq/125-lan09:45:110
29718991615,1cyclictest59550irq/125-lan09:00:180
29718991615,1cyclictest59550irq/125-lan08:25:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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