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2026-01-13 - 15:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Tue Jan 13, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28171991918,1cyclictest59550irq/125-lan09:15:122
28171991817,1cyclictest59550irq/125-lan10:20:172
28171991717,0cyclictest59550irq/125-lan10:00:192
28171991717,0cyclictest59550irq/125-lan08:40:152
28171991717,0cyclictest59550irq/125-lan08:07:502
28171991716,1cyclictest59550irq/125-lan12:32:032
28171991716,1cyclictest59550irq/125-lan11:30:172
28171991716,1cyclictest59550irq/125-lan11:25:202
28171991716,1cyclictest59550irq/125-lan10:45:112
28171991716,1cyclictest59550irq/125-lan10:25:132
28171991716,1cyclictest59550irq/125-lan09:22:482
28171991715,1cyclictest59550irq/125-lan07:10:222
28171991616,0cyclictest59550irq/125-lan09:40:212
28171991616,0cyclictest59550irq/125-lan07:45:192
28171991615,1cyclictest59550irq/125-lan12:05:152
28171991615,1cyclictest59550irq/125-lan11:49:272
28171991615,1cyclictest59550irq/125-lan11:35:172
28171991615,1cyclictest59550irq/125-lan11:00:202
28171991615,1cyclictest59550irq/125-lan10:55:142
28171991615,1cyclictest59550irq/125-lan10:40:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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