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2026-01-15 - 04:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Thu Jan 15, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24197991918,1cyclictest59550irq/125-lan20:15:172
24197991817,1cyclictest59550irq/125-lan22:50:112
24197991817,1cyclictest59550irq/125-lan22:05:172
24197991817,1cyclictest59550irq/125-lan21:20:222
24197991817,1cyclictest59550irq/125-lan20:05:122
24197991817,1cyclictest59550irq/125-lan19:10:122
24197991717,0cyclictest59550irq/125-lan22:18:082
24197991717,0cyclictest59550irq/125-lan21:15:182
24197991717,0cyclictest59550irq/125-lan20:35:132
24197991717,0cyclictest59550irq/125-lan00:18:342
24197991716,1cyclictest59550irq/125-lan23:50:212
24197991716,1cyclictest59550irq/125-lan21:05:152
24197991716,1cyclictest59550irq/125-lan19:35:182
24197991716,1cyclictest59550irq/125-lan00:20:162
24197991616,0cyclictest59550irq/125-lan23:15:192
24197991615,1cyclictest59550irq/125-lan23:20:102
24197991615,1cyclictest59550irq/125-lan22:25:172
24197991615,1cyclictest59550irq/125-lan22:10:122
24197991615,1cyclictest59550irq/125-lan19:45:152
24197991615,1cyclictest59550irq/125-lan19:15:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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