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2026-02-14 - 14:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Feb 14, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9670991817,1cyclictest59550irq/125-lan22:55:193
9670991817,1cyclictest59550irq/125-lan22:50:173
9670991817,1cyclictest59550irq/125-lan22:30:203
9670991817,1cyclictest59550irq/125-lan21:00:183
9670991817,1cyclictest59550irq/125-lan20:30:173
9670991817,1cyclictest59550irq/125-lan19:50:143
9670991716,1cyclictest59550irq/125-lan23:35:113
9670991716,1cyclictest59550irq/125-lan23:05:163
9670991716,1cyclictest59550irq/125-lan21:35:133
9670991716,1cyclictest59550irq/125-lan21:10:113
9670991716,1cyclictest59550irq/125-lan20:14:563
9670991716,1cyclictest59550irq/125-lan19:49:023
9670991716,1cyclictest59550irq/125-lan19:15:133
9670991716,1cyclictest59550irq/125-lan00:20:133
9670991616,0cyclictest59550irq/125-lan23:55:173
9670991616,0cyclictest59550irq/125-lan23:15:123
9670991616,0cyclictest59550irq/125-lan20:16:043
9670991616,0cyclictest59550irq/125-lan00:18:173
9670991616,0cyclictest59550irq/125-lan00:10:123
9670991615,1cyclictest59550irq/125-lan22:45:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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