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2026-04-06 - 09:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Mon Apr 06, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9813991816,1cyclictest59550irq/125-lan19:20:133
9813991716,1cyclictest59550irq/125-lan23:10:123
9813991716,1cyclictest59550irq/125-lan22:40:143
9813991716,1cyclictest59550irq/125-lan21:56:023
9813991716,1cyclictest59550irq/125-lan21:00:153
9813991716,1cyclictest59550irq/125-lan20:35:203
9813991716,1cyclictest59550irq/125-lan19:20:003
9813991616,0cyclictest59550irq/125-lan00:25:183
9813991615,1cyclictest59550irq/125-lan23:31:253
9813991615,1cyclictest59550irq/125-lan22:30:173
9813991615,1cyclictest59550irq/125-lan22:10:203
9813991615,1cyclictest59550irq/125-lan21:45:153
9813991615,1cyclictest59550irq/125-lan21:30:113
9813991615,1cyclictest59550irq/125-lan21:05:173
9813991615,1cyclictest59550irq/125-lan20:55:193
9813991615,1cyclictest59550irq/125-lan19:50:113
9813991615,1cyclictest59550irq/125-lan00:10:233
9813991515,0cyclictest59550irq/125-lan23:44:293
9813991515,0cyclictest59550irq/125-lan21:40:393
9813991515,0cyclictest59550irq/125-lan19:34:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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