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2026-02-21 - 06:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Feb 21, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15559991918,1cyclictest59550irq/125-lan21:45:141
15559991918,1cyclictest59550irq/125-lan00:15:151
15559991817,1cyclictest59550irq/125-lan22:40:161
15559991817,1cyclictest59550irq/125-lan20:00:191
15559991717,0cyclictest59550irq/125-lan23:36:251
15559991717,0cyclictest59550irq/125-lan21:16:161
15559991716,1cyclictest59550irq/125-lan23:05:141
15559991716,1cyclictest59550irq/125-lan22:00:121
15559991716,1cyclictest59550irq/125-lan20:35:121
15559991716,1cyclictest59550irq/125-lan20:20:121
15559991716,1cyclictest59550irq/125-lan19:20:151
15559991716,1cyclictest59550irq/125-lan00:30:131
15559991616,0cyclictest59550irq/125-lan22:05:161
15559991616,0cyclictest59550irq/125-lan21:20:181
15559991615,1cyclictest59550irq/125-lan23:00:161
15559991615,1cyclictest59550irq/125-lan22:55:131
15559991615,1cyclictest59550irq/125-lan21:30:141
15559991615,1cyclictest59550irq/125-lan19:15:131
15559991615,1cyclictest59550irq/125-lan00:25:121
15559991615,1cyclictest59550irq/125-lan00:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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