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2026-01-02 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Fri Jan 02, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30562991817,1cyclictest59550irq/125-lan12:04:412
30562991817,1cyclictest59550irq/125-lan11:25:192
30562991817,1cyclictest59550irq/125-lan09:20:132
30562991817,1cyclictest59550irq/125-lan08:55:232
30562991817,1cyclictest59550irq/125-lan08:50:162
30557991818,0cyclictest16773-21cat07:55:131
30562991717,0cyclictest59550irq/125-lan10:40:422
30562991717,0cyclictest59550irq/125-lan07:24:522
30562991716,1cyclictest59550irq/125-lan12:16:432
30562991716,1cyclictest59550irq/125-lan10:30:222
30562991716,1cyclictest59550irq/125-lan10:15:192
30562991716,1cyclictest59550irq/125-lan10:00:092
30562991716,1cyclictest59550irq/125-lan07:55:202
30562991716,1cyclictest59550irq/125-lan07:10:182
30565991616,0cyclictest2515-21fwupd11:16:423
30562991616,0cyclictest59550irq/125-lan10:10:202
30562991616,0cyclictest59550irq/125-lan09:00:132
30562991615,1cyclictest59550irq/125-lan11:45:192
30562991615,1cyclictest59550irq/125-lan09:55:162
30562991615,1cyclictest59550irq/125-lan09:15:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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