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2026-08-20 - 22:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Thu Aug 20, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30124991918,1cyclictest59550irq/125-lan11:00:500
30124991918,1cyclictest59550irq/125-lan10:47:410
30124991818,0cyclictest59550irq/125-lan12:33:270
30124991818,0cyclictest59550irq/125-lan12:25:550
30124991818,0cyclictest59550irq/125-lan11:15:130
30124991818,0cyclictest59550irq/125-lan09:55:170
30124991817,1cyclictest59550irq/125-lan12:20:010
30124991817,1cyclictest59550irq/125-lan11:35:150
30124991817,1cyclictest59550irq/125-lan11:30:120
30124991817,1cyclictest59550irq/125-lan10:34:120
30124991817,1cyclictest59550irq/125-lan09:41:040
30124991817,1cyclictest59550irq/125-lan09:28:030
30124991817,1cyclictest59550irq/125-lan09:15:560
30124991817,1cyclictest59550irq/125-lan09:10:160
30124991817,1cyclictest59550irq/125-lan08:45:100
30124991717,0cyclictest59550irq/125-lan12:39:170
30124991717,0cyclictest59550irq/125-lan12:05:160
30124991717,0cyclictest59550irq/125-lan11:11:430
30124991717,0cyclictest59550irq/125-lan11:05:220
30124991717,0cyclictest59550irq/125-lan10:35:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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