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2026-08-10 - 17:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Mon Aug 10, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19413991918,1cyclictest59550irq/125-lan11:50:170
19413991818,0cyclictest59550irq/125-lan11:40:590
19413991818,0cyclictest59550irq/125-lan09:25:230
19413991817,1cyclictest59550irq/125-lan10:36:140
19413991817,1cyclictest59550irq/125-lan09:05:120
19413991817,1cyclictest59550irq/125-lan08:53:130
19413991817,1cyclictest59550irq/125-lan08:20:210
19413991817,1cyclictest59550irq/125-lan07:40:170
19413991816,1cyclictest59550irq/125-lan10:05:120
19413991717,0cyclictest59550irq/125-lan12:03:400
19413991716,1cyclictest59550irq/125-lan10:55:160
19413991716,1cyclictest59550irq/125-lan10:01:520
19413991716,1cyclictest59550irq/125-lan09:55:140
19413991716,1cyclictest59550irq/125-lan09:15:150
19413991716,1cyclictest59550irq/125-lan08:00:000
19413991716,1cyclictest59550irq/125-lan07:45:130
19413991616,0cyclictest59550irq/125-lan11:17:060
19413991616,0cyclictest59550irq/125-lan07:33:110
19413991615,1cyclictest59550irq/125-lan12:40:010
19413991615,1cyclictest59550irq/125-lan12:30:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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