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2025-11-05 - 07:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Wed Nov 05, 2025 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31375993737,0cyclictest15073-21fwupd19:49:262
31375991918,1cyclictest60250irq/125-lan21:39:072
31375991818,0cyclictest60250irq/125-lan22:41:232
31375991817,1cyclictest60250irq/125-lan23:20:112
31375991817,1cyclictest60250irq/125-lan22:25:222
31375991817,1cyclictest60250irq/125-lan22:25:222
31375991817,1cyclictest60250irq/125-lan20:35:152
31375991817,1cyclictest60250irq/125-lan19:37:422
31375991817,1cyclictest60250irq/125-lan00:35:192
31375991816,1cyclictest60250irq/125-lan00:20:152
31375991717,0cyclictest60250irq/125-lan20:40:492
31375991717,0cyclictest60250irq/125-lan00:17:462
31375991716,1cyclictest60250irq/125-lan23:30:212
31375991716,1cyclictest60250irq/125-lan21:05:562
31375991716,1cyclictest60250irq/125-lan20:50:212
31375991716,1cyclictest60250irq/125-lan20:50:202
31375991716,1cyclictest60250irq/125-lan20:15:222
31375991716,1cyclictest60250irq/125-lan19:55:172
31375991616,0cyclictest60250irq/125-lan23:50:132
31375991616,0cyclictest60250irq/125-lan19:50:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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