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2026-06-22 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Mon Jun 22, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27147991918,1cyclictest59550irq/125-lan07:16:210
27147991818,0cyclictest59550irq/125-lan10:55:000
27147991817,1cyclictest59550irq/125-lan11:15:200
27147991717,0cyclictest59550irq/125-lan10:19:490
27147991717,0cyclictest59550irq/125-lan10:00:010
27147991717,0cyclictest59550irq/125-lan08:55:110
27147991716,1cyclictest59550irq/125-lan12:20:100
27147991716,1cyclictest59550irq/125-lan12:01:400
27147991716,1cyclictest59550irq/125-lan09:30:100
27147991716,1cyclictest59550irq/125-lan09:25:140
27147991716,1cyclictest59550irq/125-lan09:20:180
27147991716,1cyclictest59550irq/125-lan07:50:140
27147991716,1cyclictest59550irq/125-lan07:45:180
27147991615,1cyclictest59550irq/125-lan12:37:400
27147991615,1cyclictest59550irq/125-lan12:10:120
27147991615,1cyclictest59550irq/125-lan11:50:120
27147991615,1cyclictest59550irq/125-lan10:10:170
27147991615,1cyclictest59550irq/125-lan09:15:310
27147991615,1cyclictest59550irq/125-lan08:45:200
27147991615,1cyclictest59550irq/125-lan08:35:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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