You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-14 - 09:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Tue Jul 14, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12803991918,1cyclictest59550irq/125-lan22:35:190
12803991918,1cyclictest59550irq/125-lan22:00:130
12803991918,1cyclictest59550irq/125-lan20:25:130
12803991818,0cyclictest59550irq/125-lan20:55:150
12803991818,0cyclictest59550irq/125-lan00:09:010
12803991817,1cyclictest59550irq/125-lan20:40:130
12803991817,1cyclictest59550irq/125-lan00:37:290
12803991717,0cyclictest59550irq/125-lan23:00:210
12803991717,0cyclictest59550irq/125-lan22:33:230
12803991717,0cyclictest59550irq/125-lan22:23:130
12803991717,0cyclictest59550irq/125-lan21:06:190
12803991716,1cyclictest59550irq/125-lan23:55:210
12803991716,1cyclictest59550irq/125-lan23:15:160
12803991716,1cyclictest59550irq/125-lan22:05:200
12803991716,1cyclictest59550irq/125-lan20:50:140
12803991716,1cyclictest59550irq/125-lan19:30:140
12803991716,1cyclictest59550irq/125-lan19:20:210
12803991716,1cyclictest59550irq/125-lan00:15:120
12803991716,1cyclictest59550irq/125-lan00:10:160
12803991716,1cyclictest59550irq/125-lan00:00:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional