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2026-09-20 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sun Sep 20, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4994991919,0cyclictest59550irq/125-lan22:56:050
4994991919,0cyclictest59550irq/125-lan00:05:170
4994991918,1cyclictest59550irq/125-lan23:40:330
4994991918,1cyclictest59550irq/125-lan22:18:380
4994991918,1cyclictest59550irq/125-lan21:44:250
4994991918,1cyclictest59550irq/125-lan21:32:470
4994991918,1cyclictest59550irq/125-lan00:04:320
4994991818,0cyclictest59550irq/125-lan23:49:070
4994991818,0cyclictest59550irq/125-lan22:35:120
4994991818,0cyclictest59550irq/125-lan22:12:330
4994991818,0cyclictest59550irq/125-lan21:50:300
4994991818,0cyclictest59550irq/125-lan21:39:320
4994991817,1cyclictest59550irq/125-lan23:28:360
4994991817,1cyclictest59550irq/125-lan23:20:180
4994991817,1cyclictest59550irq/125-lan23:15:050
4994991817,1cyclictest59550irq/125-lan23:14:510
4994991817,1cyclictest59550irq/125-lan23:00:120
4994991817,1cyclictest59550irq/125-lan22:45:500
4994991817,1cyclictest59550irq/125-lan22:40:190
4994991817,1cyclictest59550irq/125-lan22:30:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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