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2026-01-12 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Mon Jan 12, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3051991817,1cyclictest59550irq/125-lan11:20:002
3051991817,1cyclictest59550irq/125-lan10:55:142
3051991817,1cyclictest59550irq/125-lan08:39:592
3051991817,1cyclictest59550irq/125-lan08:20:122
3051991817,1cyclictest59550irq/125-lan08:15:192
3051991817,1cyclictest59550irq/125-lan08:00:202
3051991817,1cyclictest59550irq/125-lan08:00:202
3051991716,1cyclictest59550irq/125-lan12:35:232
3051991716,1cyclictest59550irq/125-lan12:25:102
3051991716,1cyclictest59550irq/125-lan11:30:142
3051991716,1cyclictest59550irq/125-lan10:50:122
3051991716,1cyclictest59550irq/125-lan10:45:112
3051991716,1cyclictest59550irq/125-lan10:40:122
3051991716,1cyclictest59550irq/125-lan08:05:142
3051991715,2cyclictest59550irq/125-lan11:11:592
3051991616,0cyclictest59550irq/125-lan07:30:582
3051991615,1cyclictest59550irq/125-lan12:20:082
3051991615,1cyclictest59550irq/125-lan12:00:142
3051991615,1cyclictest59550irq/125-lan10:30:202
3051991615,1cyclictest59550irq/125-lan10:15:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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