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2026-08-26 - 02:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Tue Aug 25, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16566991919,0cyclictest59550irq/125-lan12:35:060
16566991918,1cyclictest59550irq/125-lan11:40:000
16566991918,1cyclictest59550irq/125-lan10:55:180
16566991918,1cyclictest59550irq/125-lan09:58:570
16566991917,1cyclictest59550irq/125-lan12:00:350
16566991917,1cyclictest59550irq/125-lan11:26:560
16566991818,0cyclictest59550irq/125-lan12:23:230
16566991818,0cyclictest59550irq/125-lan12:09:100
16566991818,0cyclictest59550irq/125-lan11:01:270
16566991818,0cyclictest59550irq/125-lan10:42:420
16566991818,0cyclictest59550irq/125-lan10:10:180
16566991818,0cyclictest59550irq/125-lan09:26:380
16566991818,0cyclictest59550irq/125-lan09:10:200
16566991817,1cyclictest59550irq/125-lan12:25:580
16566991817,1cyclictest59550irq/125-lan12:10:090
16566991817,1cyclictest59550irq/125-lan11:40:010
16566991817,1cyclictest59550irq/125-lan11:30:100
16566991817,1cyclictest59550irq/125-lan10:50:130
16566991817,1cyclictest59550irq/125-lan10:20:020
16566991817,1cyclictest59550irq/125-lan10:18:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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