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2026-01-14 - 04:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Wed Jan 14, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10661991818,0cyclictest59550irq/125-lan19:21:481
10661991818,0cyclictest59550irq/125-lan00:15:141
10661991817,1cyclictest59550irq/125-lan23:55:111
10661991817,1cyclictest59550irq/125-lan23:00:111
10661991817,1cyclictest59550irq/125-lan22:45:111
10661991817,1cyclictest59550irq/125-lan21:40:191
10661991817,1cyclictest59550irq/125-lan20:50:181
10661991817,1cyclictest59550irq/125-lan20:20:201
10661991817,1cyclictest59550irq/125-lan00:30:121
10661991717,0cyclictest59550irq/125-lan23:19:481
10661991717,0cyclictest59550irq/125-lan20:30:121
10661991717,0cyclictest59550irq/125-lan19:10:561
10661991716,1cyclictest59550irq/125-lan21:15:131
10661991716,1cyclictest59550irq/125-lan20:05:201
10661991716,1cyclictest59550irq/125-lan20:05:201
10661991716,1cyclictest59550irq/125-lan00:20:111
10661991616,0cyclictest59550irq/125-lan20:28:461
10661991615,1cyclictest59550irq/125-lan23:40:171
10661991615,1cyclictest59550irq/125-lan22:05:221
10661991615,1cyclictest59550irq/125-lan00:35:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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