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2026-08-29 - 23:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat Aug 29, 2026 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6579991919,0cyclictest59550irq/125-lan12:21:510
6579991919,0cyclictest59550irq/125-lan11:36:140
6579991918,1cyclictest59550irq/125-lan12:28:020
6579991918,1cyclictest59550irq/125-lan12:11:460
6579991918,1cyclictest59550irq/125-lan11:47:150
6579991918,1cyclictest59550irq/125-lan11:05:240
6579991918,1cyclictest59550irq/125-lan10:39:170
6579991918,1cyclictest59550irq/125-lan10:27:220
6579991918,1cyclictest59550irq/125-lan07:45:200
6579991818,0cyclictest59550irq/125-lan12:18:370
6579991818,0cyclictest59550irq/125-lan12:03:510
6579991818,0cyclictest59550irq/125-lan11:23:280
6579991818,0cyclictest59550irq/125-lan10:46:100
6579991818,0cyclictest59550irq/125-lan09:50:020
6579991818,0cyclictest59550irq/125-lan09:39:240
6579991818,0cyclictest59550irq/125-lan09:20:330
6579991818,0cyclictest59550irq/125-lan08:10:130
6579991817,1cyclictest59550irq/125-lan12:32:180
6579991817,1cyclictest59550irq/125-lan12:05:150
6579991817,1cyclictest59550irq/125-lan11:58:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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