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2022-12-08 - 20:49

x86 Intel Celeron G1620 @2700 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #8, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Wed Dec 07, 2022 12:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
785699190,1cyclictest0-21swapper/109:22:591
785699170,16cyclictest20350-21x2golistsession12:37:511
785699170,0cyclictest0-21swapper/109:43:451
785599170,17cyclictest0-21swapper/010:21:310
785699160,15cyclictest7007-21ssh11:10:461
7856991515,0cyclictest0-21swapper/111:20:411
7856991514,0cyclictest0-21swapper/107:57:001
785699150,0cyclictest0-21swapper/112:14:051
7855991514,0cyclictest0-21swapper/011:40:110
7855991513,1cyclictest18912-21pmu-power11:20:240
785599150,15cyclictest0-21swapper/012:28:000
785699140,13cyclictest0-21swapper/111:40:021
785699140,13cyclictest0-21swapper/110:52:011
785599149,4cyclictest492-21x2golistsession11:56:420
7855991414,0cyclictest0-21swapper/010:56:210
7855991412,1cyclictest13619-21diskmemload09:41:260
785599140,13cyclictest0-21swapper/007:15:210
7856991313,0cyclictest0-21swapper/111:45:201
7856991313,0cyclictest0-21swapper/109:52:251
785699130,0cyclictest0-21swapper/107:18:121
7855991313,0cyclictest0-21swapper/008:51:310
7855991311,1cyclictest0-21swapper/011:39:520
7856991212,0cyclictest0-21swapper/111:55:171
7856991212,0cyclictest0-21swapper/111:50:181
7856991212,0cyclictest0-21swapper/110:13:211
7856991212,0cyclictest0-21swapper/107:43:151
7856991210,1cyclictest8470-21ssh10:21:131
785699120,12cyclictest0-21swapper/112:25:221
785699120,12cyclictest0-21swapper/111:39:221
785599120,12cyclictest0-21swapper/012:15:410
785599120,12cyclictest0-21swapper/010:48:510
785599120,12cyclictest0-21swapper/009:28:010
785599120,0cyclictest0-21swapper/011:30:210
785599120,0cyclictest0-21swapper/007:45:210
7856991111,0cyclictest0-21swapper/112:06:221
7856991111,0cyclictest0-21swapper/110:02:591
7856991111,0cyclictest0-21swapper/109:55:521
7856991111,0cyclictest0-21swapper/109:15:411
785699110,11cyclictest0-21swapper/112:20:021
785599115,1cyclictest11026-21apt08:10:000
7855991111,0cyclictest0-21swapper/012:23:110
7855991111,0cyclictest0-21swapper/010:00:010
7855991111,0cyclictest0-21swapper/009:20:210
7855991111,0cyclictest0-21swapper/008:28:420
785599110,11cyclictest0-21swapper/010:37:410
785699108,1cyclictest632-21irqbalance10:25:011
785699106,3cyclictest26838-21ssh11:26:281
785699106,3cyclictest1373-21users10:15:271
785699105,4cyclictest7217-21ssh12:02:001
7856991010,0cyclictest0-21swapper/111:07:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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