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2026-03-05 - 23:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Thu Mar 05, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24346991817,1cyclictest59550irq/125-lan12:05:141
24346991817,1cyclictest59550irq/125-lan08:30:101
24346991817,1cyclictest59550irq/125-lan07:40:211
24346991717,0cyclictest59550irq/125-lan09:14:371
24346991717,0cyclictest59550irq/125-lan09:01:361
24346991717,0cyclictest59550irq/125-lan08:35:001
24346991716,1cyclictest59550irq/125-lan12:25:191
24346991716,1cyclictest59550irq/125-lan10:35:111
24346991716,1cyclictest59550irq/125-lan07:25:121
24346991616,0cyclictest59550irq/125-lan11:00:171
24346991616,0cyclictest59550irq/125-lan10:45:161
24346991616,0cyclictest59550irq/125-lan10:15:371
24346991616,0cyclictest59550irq/125-lan08:14:081
24346991616,0cyclictest59550irq/125-lan08:00:211
24346991615,1cyclictest59550irq/125-lan11:30:121
24346991615,1cyclictest59550irq/125-lan11:25:531
24346991615,1cyclictest59550irq/125-lan10:00:181
24346991615,1cyclictest59550irq/125-lan08:15:171
24346991614,1cyclictest59550irq/125-lan11:10:111
24346991515,0cyclictest59550irq/125-lan12:10:011
24346991514,1cyclictest59550irq/125-lan12:30:151
24346991514,1cyclictest59550irq/125-lan11:40:141
24346991514,1cyclictest59550irq/125-lan11:35:131
24346991514,1cyclictest59550irq/125-lan11:15:161
24346991514,1cyclictest59550irq/125-lan11:10:011
24346991514,1cyclictest59550irq/125-lan10:50:171
24346991514,1cyclictest59550irq/125-lan10:30:181
24346991514,1cyclictest59550irq/125-lan10:20:161
24346991514,1cyclictest59550irq/125-lan09:55:111
24346991514,1cyclictest59550irq/125-lan09:25:171
24346991514,1cyclictest59550irq/125-lan09:05:201
24346991514,1cyclictest59550irq/125-lan08:55:131
24346991514,1cyclictest59550irq/125-lan08:05:201
24346991514,1cyclictest59550irq/125-lan07:35:111
24346991514,1cyclictest59550irq/125-lan07:20:181
24346991414,0cyclictest59550irq/125-lan11:50:141
24346991414,0cyclictest325-21hwrng09:36:291
24346991413,1cyclictest59550irq/125-lan12:15:121
24346991413,1cyclictest59550irq/125-lan10:05:011
24346991413,1cyclictest59550irq/125-lan09:50:161
24346991413,1cyclictest59550irq/125-lan08:40:191
24351991313,0cyclictest325-21hwrng10:58:232
24351991313,0cyclictest325-21hwrng07:42:492
24346991313,0cyclictest59550irq/125-lan07:54:591
24346991312,1cyclictest59550irq/125-lan09:40:201
24355991212,0cyclictest325-21hwrng10:12:193
24351991212,0cyclictest325-21hwrng09:23:102
24346991212,0cyclictest59550irq/125-lan12:00:011
24346991212,0cyclictest59550irq/125-lan09:15:131
24346991211,1cyclictest59550irq/125-lan12:35:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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