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2026-01-19 - 10:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Mon Jan 19, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20484991818,0cyclictest59550irq/125-lan20:40:282
20484991717,0cyclictest59550irq/125-lan21:35:172
20484991716,1cyclictest59550irq/125-lan19:30:112
20484991616,0cyclictest59550irq/125-lan23:50:112
20484991616,0cyclictest59550irq/125-lan22:21:092
20484991616,0cyclictest59550irq/125-lan20:20:162
20484991616,0cyclictest59550irq/125-lan19:55:152
20484991616,0cyclictest59550irq/125-lan19:45:182
20484991616,0cyclictest59550irq/125-lan19:37:102
20484991616,0cyclictest59550irq/125-lan00:22:252
20484991616,0cyclictest59550irq/125-lan00:15:122
20484991615,1cyclictest59550irq/125-lan23:45:122
20484991615,1cyclictest59550irq/125-lan23:00:142
20473991616,0cyclictest24040-21fwupd19:15:420
20484991515,0cyclictest59550irq/125-lan23:25:202
20484991515,0cyclictest59550irq/125-lan23:15:172
20484991515,0cyclictest59550irq/125-lan22:50:122
20484991515,0cyclictest59550irq/125-lan20:19:092
20484991515,0cyclictest59550irq/125-lan20:19:092
20484991515,0cyclictest59550irq/125-lan20:05:132
20484991515,0cyclictest59550irq/125-lan00:35:142
20484991515,0cyclictest59550irq/125-lan00:10:142
20484991515,0cyclictest325-21hwrng22:30:432
20484991515,0cyclictest325-21hwrng21:55:542
20484991514,1cyclictest59550irq/125-lan21:05:172
20484991514,1cyclictest59550irq/125-lan20:50:182
20484991514,1cyclictest59550irq/125-lan19:15:122
20484991414,0cyclictest59550irq/125-lan22:55:112
20484991414,0cyclictest59550irq/125-lan22:35:112
20484991414,0cyclictest59550irq/125-lan21:50:192
20484991414,0cyclictest59550irq/125-lan21:00:162
20484991414,0cyclictest59550irq/125-lan20:55:132
20484991414,0cyclictest59550irq/125-lan20:35:192
20484991414,0cyclictest59550irq/125-lan19:20:232
20484991414,0cyclictest59550irq/125-lan00:30:202
20484991414,0cyclictest59550irq/125-lan00:00:122
20484991414,0cyclictest325-21hwrng22:29:422
20484991413,1cyclictest59550irq/125-lan21:30:132
20484991313,0cyclictest59550irq/125-lan23:35:132
20484991313,0cyclictest59550irq/125-lan23:05:162
20484991313,0cyclictest59550irq/125-lan22:15:112
20484991313,0cyclictest59550irq/125-lan22:00:202
20484991313,0cyclictest59550irq/125-lan21:29:082
20484991313,0cyclictest59550irq/125-lan20:48:082
20484991313,0cyclictest59550irq/125-lan20:31:092
20484991313,0cyclictest59550irq/125-lan19:10:122
20484991313,0cyclictest325-21hwrng21:21:062
20480991313,0cyclictest325-21hwrng23:33:111
20480991313,0cyclictest325-21hwrng00:02:541
20484991212,0cyclictest59550irq/125-lan22:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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