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2024-04-20 - 02:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack9slot1.osadl.org (updated Sat Aug 08, 2020 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811150,0rcu_preempt7239-21at-spi-registry09:30:240
811130,0rcu_preempt27309-21kworker/0:109:57:340
811100,0rcu_preempt27743-21ssh11:31:270
811100,0rcu_preempt12081-21ssh11:53:560
811090,0rcu_preempt7260-21gdm-simple-gree11:06:400
811090,0rcu_preempt7260-21gdm-simple-gree10:16:180
811090,0rcu_preempt20555-21ssh10:36:470
811080,0rcu_preempt7260-21gdm-simple-gree09:06:290
811080,0rcu_preempt24557-21ssh12:12:350
811070,0rcu_preempt7260-21gdm-simple-gree10:24:200
811070,0rcu_preempt24719-21ssh11:27:420
811070,0rcu_preempt11962-1kworker/0:1H10:29:490
2111070,0ktimersoftd/172815pulseaudio12:15:531
811060,0rcu_preempt7127-21Xorg10:39:520
811060,0rcu_preempt16614-21ssh09:02:390
811050,0rcu_preempt7260-21gdm-simple-gree10:08:480
811050,0rcu_preempt3-21ksoftirqd/008:13:080
811040,0rcu_preempt7127-21Xorg11:12:570
811030,0rcu_preempt3392-21rm11:42:570
811030,0rcu_preempt31659-21ssh09:22:560
811030,0rcu_preempt27309-21kworker/0:108:50:530
811030,0rcu_preempt17179-21ssh09:47:360
811020,0rcu_preempt7260-21gdm-simple-gree12:17:190
811020,0rcu_preempt7239-21at-spi-registry09:18:130
811010,0rcu_preempt7940-1kworker/0:1H11:51:590
811010,0rcu_preempt7239-21at-spi-registry09:11:530
811000,0rcu_preempt23162-1kworker/0:2H09:39:420
81980,0rcu_preempt11953-21kworker/1:010:25:001
81980,0rcu_preempt0-21swapper/010:44:520
81960,0rcu_preempt8884-21snmpd11:34:240
81960,0rcu_preempt8685-1kworker/0:2H11:21:270
81930,0rcu_preempt7127-21Xorg10:19:060
81930,0rcu_preempt18201-21kworker/1:009:10:131
81920,0rcu_preempt4548-21kworker/1:209:37:281
81920,0rcu_preempt22361-21kworker/1:208:15:351
81920,0rcu_preempt0-21swapper/110:47:391
81910,0rcu_preempt30971-21kworker/1:009:24:041
81910,0rcu_preempt17043-21kworker/1:210:50:191
81900,0rcu_preempt8286-21kworker/1:210:22:541
81900,0rcu_preempt22361-21kworker/1:208:26:531
81900,0rcu_preempt22361-21kworker/1:207:59:451
81900,0rcu_preempt22361-21kworker/1:206:47:271
81900,0rcu_preempt16619-21kworker/1:111:19:081
81890,0rcu_preempt4548-21kworker/1:209:32:101
81890,0rcu_preempt27230-21kworker/1:111:34:061
81890,0rcu_preempt22361-21kworker/1:209:01:531
81890,0rcu_preempt22361-21kworker/1:208:09:281
81890,0rcu_preempt22361-21kworker/1:206:59:551
81890,0rcu_preempt22-21ksoftirqd/111:31:311
81890,0rcu_preempt22-21ksoftirqd/110:12:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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