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2025-06-28 - 23:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Sat Jun 28, 2025 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154792310271,25sleep00-21swapper/00
155342298236,50sleep20-21swapper/22
156942292181,41sleep10-21swapper/11
154572255177,24sleep30-21swapper/33
1587899193187,4cyclictest24535-21perf1
1587199188182,4cyclictest24516-21munin-run0
1588699181175,4cyclictest24536-21idleruntime-cro3
1588299158155,2cyclictest0-21swapper/22
241772560,2sleep00-21swapper/00
289852550,4sleep10-21swapper/11
212682530,1sleep30-21swapper/33
78052460,1sleep20-21swapper/22
204482308,18sleep30-21swapper/33
15886992517,5cyclictest505-21dbus-daemon3
15878992419,3cyclictest6412-21basename1
179962230,12sleep228-21ksoftirqd/22
15886992316,4cyclictest9715-21cron3
1588299237,15cyclictest111rcu_preempt2
15878992316,4cyclictest19817-21sh1
15871992317,4cyclictest19605-21cut0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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