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2025-08-29 - 14:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Fri Aug 29, 2025 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1524999275271,2cyclictest0-21swapper/33
149782253181,24sleep30-21swapper/33
148282250183,35sleep00-21swapper/00
150132245178,53sleep10-21swapper/11
149942235198,24sleep20-21swapper/22
1524499178172,4cyclictest17199-21apt2
1523599161156,3cyclictest505-21dbus-daemon0
1523999149142,4cyclictest1-21systemd1
261721290,3sleep21524499cyclictest2
137752680,1sleep10-21swapper/11
309402600,2sleep21524499cyclictest2
103192600,4sleep31524999cyclictest3
84792420,1sleep30-21swapper/33
260402400,3sleep30-21swapper/33
1523599342,3cyclictest111rcu_preempt0
1524499331,6cyclictest271rcuc/22
1523999320,30cyclictest6748-21kworker/1:21
1523599311,5cyclictest0-21swapper/00
1523599311,5cyclictest0-21swapper/00
15244992716,9cyclictest271rcuc/22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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