You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-09-15 - 06:30
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Mon Sep 15, 2025 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
281082310274,24sleep20-21swapper/22
266792298268,17sleep00-21swapper/00
2864199258254,2cyclictest0-21swapper/22
283602244210,22sleep10-21swapper/11
2863899228220,5cyclictest8925-21sendmail1
283672227190,24sleep30-21swapper/33
2864699215209,4cyclictest8954-21sendmail-msp3
2863399214208,4cyclictest8904-21munin-run0
126021280,3sleep02863399cyclictest0
51162520,2sleep00-21swapper/00
307442510,1sleep10-21swapper/11
320902480,3sleep10-21swapper/11
171022470,1sleep20-21swapper/22
161752460,1sleep30-21swapper/33
243402420,1sleep00-21swapper/00
28641994114,23cyclictest505-21dbus-daemon2
28633993924,3cyclictest9-21ksoftirqd/00
28633993924,3cyclictest9-21ksoftirqd/00
28641993511,3cyclictest28274-21sendmail-mta2
2864199350,17cyclictest305-21cat2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional