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2025-11-21 - 17:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack9slot4.osadl.org (updated Fri Nov 21, 2025 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31760991299cyclictest0-21swapper/005:16:000
31760991293cyclictest30256-21latency_hist06:05:460
31760991236cyclictest5004-21latency04:26:140
31760991208cyclictest0-21swapper/006:36:170
31760991203cyclictest19615-21latency_hist02:35:410
31544111980sleep0-21swapper/101:30:311
31760991184cyclictest13039-21latency_hist03:45:430
317609911770cyclictest30033-21latency_hist07:00:480
317609911770cyclictest30033-21latency_hist07:00:480
31760991153cyclictest27100-21latency_hist06:55:480
317609911511cyclictest0-21swapper/006:26:310
31760991149cyclictest0-21swapper/002:06:130
317609911281cyclictest6950irq/18-mmc006:06:030
31760991114cyclictest21091-21latency_hist02:40:410
317609910910cyclictest11207-21ssh04:36:240
31760991088cyclictest0-21swapper/003:51:120
31760991088cyclictest0-21swapper/001:31:180
31760991087cyclictest0-21swapper/003:57:080
31760991084cyclictest2147-21proc_pri03:21:160
317609910757cyclictest30931-21kworker/u4:204:01:120
31760991073cyclictest18989-21diskstats05:46:050
317609910726cyclictest33950irq/43-eth004:25:440
31760991064cyclictest12442-21latency_hist06:30:480
317609910558cyclictest7073-21latency_hist01:55:400
317609910551cyclictest4230-21diskmemload04:45:440
31760991048cyclictest0-21swapper/004:46:100
31760991048cyclictest0-21swapper/003:36:120
317609910462cyclictest6950irq/18-mmc005:51:190
317609910440cyclictest0-21swapper/005:36:360
31760991038cyclictest0-21swapper/003:48:070
31518110370sleep0-21swapper/001:30:300
31760991028cyclictest0-21swapper/006:23:370
31760991028cyclictest0-21swapper/002:05:390
31760991028cyclictest0-21swapper/001:46:080
317609910262cyclictest6950irq/18-mmc005:11:150
31760991026cyclictest2672-21latency_hist03:25:410
31760991024cyclictest304-21snmpd04:06:130
317609910210cyclictest0-21swapper/006:47:470
31760991014cyclictest18570-21latency_hist05:45:460
317609910065cyclictest6950irq/18-mmc006:45:480
31760991003cyclictest29665-21kworker/u4:106:11:000
317609910010cyclictest30431-21latency_hist05:10:440
3176099998cyclictest0-21swapper/005:31:150
3176099996cyclictest4826-21open_files06:16:220
3176099996cyclictest19634-21irqstats04:51:140
31760999812cyclictest28815-21ntp_states04:11:170
3176099978cyclictest0-21swapper/001:45:390
3176099978cyclictest0-21swapper/001:45:390
3176099968cyclictest0-21swapper/002:26:090
3176099959cyclictest0-21swapper/002:31:050
3176099957cyclictest0-21swapper/005:02:090
3176099957cyclictest0-21swapper/005:02:090
3176099949cyclictest0-21swapper/001:56:090
31760999437cyclictest0-21swapper/005:21:300
31760999410cyclictest0-21swapper/005:30:460
3176099939cyclictest0-21swapper/003:01:110
3176099933cyclictest32025-21latency_hist03:15:410
31760999282cyclictest6950irq/18-mmc004:30:490
31760999269cyclictest0-21swapper/003:16:150
3176099924cyclictest16447-21cat02:25:400
3176099918cyclictest0-21swapper/005:56:260
3176099918cyclictest0-21swapper/005:56:260
3176099918cyclictest0-21swapper/002:20:060
31760999154cyclictest31655-21missed_timers04:16:140
3176099909cyclictest0-21swapper/002:55:560
3176099909cyclictest0-21swapper/002:55:560
31760999067cyclictest0-21swapper/003:31:220
3176099906cyclictest0-21swapper/001:35:570
31760999049cyclictest0-21swapper/002:55:410
31760998980cyclictest6950irq/18-mmc004:56:000
31760998914cyclictest0-21swapper/003:08:110
3176099879cyclictest0-21swapper/002:11:340
31760998616cyclictest0-21swapper/002:46:100
22150810irq/18-spi_topc3176799cyclictest05:30:161
22150690irq/18-spi_topc3176799cyclictest06:23:371
22150690irq/18-spi_topc3176799cyclictest05:18:351
3176799669cyclictest0-21swapper/106:26:161
3176799669cyclictest0-21swapper/103:21:141
3176799659cyclictest0-21swapper/105:06:031
3176799659cyclictest0-21swapper/105:01:171
3176799659cyclictest0-21swapper/105:01:171
3176799659cyclictest0-21swapper/102:30:541
22150650irq/18-spi_topc3176799cyclictest06:51:171
3176799649cyclictest0-21swapper/104:05:201
3176799648cyclictest0-21swapper/105:51:211
3176799648cyclictest0-21swapper/103:51:181
3176799648cyclictest0-21swapper/103:28:591
3176799639cyclictest0-21swapper/106:44:441
3176799639cyclictest0-21swapper/105:46:031
3176799639cyclictest0-21swapper/104:14:201
3176799638cyclictest0-21swapper/106:46:051
3176799638cyclictest0-21swapper/102:41:141
31767996324cyclictest0-21swapper/106:36:381
3176799628cyclictest0-21swapper/104:10:011
3176799628cyclictest0-21swapper/102:16:171
22150620irq/18-spi_topc3176799cyclictest05:40:411
3176799618cyclictest0-21swapper/103:43:481
3176799618cyclictest0-21swapper/103:35:561
3176799618cyclictest0-21swapper/102:56:131
3176799618cyclictest0-21swapper/102:56:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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