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2026-03-17 - 07:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack9slot4.osadl.org (updated Tue Mar 17, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
221951137107sleep0-21swapper/105:40:021
22336991158cyclictest0-21swapper/008:55:420
22336991126cyclictest0-21swapper/009:18:380
22336991097cyclictest0-21swapper/009:35:420
22336991078cyclictest0-21swapper/008:35:360
22336991077cyclictest0-21swapper/008:11:390
22073110771sleep0-21swapper/005:39:580
2233699999cyclictest0-21swapper/006:55:320
2233699997cyclictest0-21swapper/006:26:580
22336999518cyclictest0-21swapper/010:25:450
2233699939cyclictest0-21swapper/006:11:080
2233699927cyclictest0-21swapper/010:30:050
2233699907cyclictest0-21swapper/008:25:270
22336999010cyclictest0-21swapper/010:21:000
22336999010cyclictest0-21swapper/010:21:000
2233699898cyclictest0-21swapper/009:24:020
2233699878cyclictest0-21swapper/007:35:450
2233699877cyclictest0-21swapper/010:55:000
2233699877cyclictest0-21swapper/009:50:370
2233699877cyclictest0-21swapper/006:38:070
2233699868cyclictest0-21swapper/005:40:110
2233699867cyclictest0-21swapper/007:26:390
2233699867cyclictest0-21swapper/007:26:390
2233699859cyclictest0-21swapper/006:15:540
2233699857cyclictest0-21swapper/011:00:090
2233699857cyclictest0-21swapper/006:23:070
23550830irq/18-spi_topc2234299cyclictest10:57:591
2233699838cyclictest0-21swapper/006:40:310
2233699837cyclictest0-21swapper/007:55:300
22336998258cyclictest0-21swapper/006:05:350
22336998158cyclictest0-21swapper/011:05:450
22336998154cyclictest0-21swapper/009:00:430
2233699808cyclictest0-21swapper/007:50:510
2233699807cyclictest0-21swapper/008:00:260
6950790irq/18-mmc00-21swapper/008:35:000
2233699799cyclictest0-21swapper/006:30:460
2233699798cyclictest0-21swapper/006:50:530
23550780irq/18-spi_topc2234299cyclictest09:05:081
2233699788cyclictest0-21swapper/007:46:450
2233699788cyclictest0-21swapper/007:46:450
22336997869cyclictest5350irq/18-pch-dma08:50:280
2233699778cyclictest0-21swapper/010:40:350
2233699777cyclictest0-21swapper/010:10:410
2233699777cyclictest0-21swapper/009:55:410
2233699768cyclictest0-21swapper/010:50:390
2233699767cyclictest0-21swapper/009:40:120
2233699767cyclictest0-21swapper/009:30:120
2233699767cyclictest0-21swapper/007:40:290
1499760migration/010988-21aten_r9power_cu10:15:210
2233699758cyclictest0-21swapper/009:05:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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