You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-11 - 04:13

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #9, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack9slot4s (updated Wed Mar 11, 2026 00:59:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
161829911601136,19cyclictest0-21swapper/019:26:190
158962647540,31sleep00-21swapper/019:22:340
160732633588,31sleep10-21swapper/119:24:251
1618399198189,6cyclictest0-21swapper/119:26:201
291832970,8sleep11618399cyclictest22:55:171
31292900,8sleep01618299cyclictest00:09:230
111082870,7sleep10-21swapper/122:02:551
49112830,4sleep04909-21df22:30:130
205022820,4sleep1201rcuc/122:12:311
103782810,3sleep0111rcuc/023:09:480
319282690,5sleep0111rcuc/020:05:000
56202630,7sleep10-21swapper/121:24:071
224232461,32sleep122536-21cut19:40:011
233522450,8sleep11618399cyclictest23:55:511
1618399441,14cyclictest0-21swapper/121:27:061
1618299442,18cyclictest0-21swapper/022:47:130
48442421,37sleep14854-21ssh23:03:461
1618399425,18cyclictest4370-21ssh00:10:161
16183994210,6cyclictest295952rm21:48:501
1618399398,28cyclictest0-21swapper/123:36:151
1618399386,5cyclictest81rcu_preempt00:52:261
1618399386,5cyclictest81rcu_preempt00:52:261
1618399385,5cyclictest81rcu_preempt23:05:091
1618299385,7cyclictest445-21rm23:32:390
1618299384,31cyclictest0-21swapper/022:39:560
113372380,6sleep111331-21ssh21:30:101
92642370,4sleep1201rcuc/120:30:131
92642370,4sleep1201rcuc/120:30:121
1618399376,4cyclictest81rcu_preempt20:10:141
16183993728,5cyclictest25388-21kworker/1:222:25:351
1618299374,29cyclictest0-21swapper/022:19:550
16182993728,5cyclictest30876-21ssh22:56:360
1618299371,23cyclictest5182-21ssh23:04:140
16183993627,5cyclictest32294-21ssh00:39:351
1618399362,5cyclictest27710-21grep22:20:151
1618399354,3cyclictest0-21swapper/123:23:351
1618399352,29cyclictest0-21swapper/121:05:151
16182993527,5cyclictest2403-21irqbalance22:26:360
1618299352,5cyclictest0-21swapper/023:25:550
1618299352,29cyclictest0-21swapper/021:11:150
1618299352,29cyclictest0-21swapper/000:13:560
1618299351,12cyclictest0-21swapper/022:02:370
325842341,29sleep132596-21ssh23:32:111
1618399345,25cyclictest0-21swapper/100:06:571
1618399345,17cyclictest0-21swapper/121:36:151
16183993428,3cyclictest0-21swapper/122:09:351
16183993425,5cyclictest22176-21ssh00:28:561
1618399341,29cyclictest31075-21fschecks_count21:50:161
1618399341,22cyclictest0-21swapper/123:54:461
1618299343,19cyclictest0-21swapper/000:45:290
16182993427,4cyclictest0-21swapper/023:10:360
1618299342,29cyclictest0-21swapper/000:21:160
1618299341,30cyclictest0-21swapper/020:53:150
1618299341,29cyclictest2403-21irqbalance23:45:560
1618299341,20cyclictest21728-21sensors19:35:280
1618299341,11cyclictest19308-21ntp_states00:25:240
261032332,27sleep10-21swapper/121:11:041
231212331,28sleep123145-21iostat22:15:211
19362330,4sleep0111rcuc/020:10:170
1618399335,4cyclictest81rcu_preempt00:02:361
1618399334,4cyclictest81rcu_preempt00:15:381
1618399332,4cyclictest81rcu_preempt23:10:161
1618399331,6cyclictest15393-21ssh23:48:161
1618399331,4cyclictest81rcu_preempt23:40:301
1618399331,4cyclictest81rcu_preempt21:41:421
1618399331,4cyclictest766-21fschecks_count00:40:161
1618399331,4cyclictest13208-21ssh22:38:561
1618299338,21cyclictest0-21swapper/022:44:190
1618299335,4cyclictest81rcu_preempt21:50:450
1618299335,14cyclictest20556-21sh22:12:380
1618299335,14cyclictest20115-21cron23:20:000
1618299333,15cyclictest19326-21hddtemp_smartct19:30:160
1618299333,14cyclictest3727-21df_inode20:15:150
16182993326,5cyclictest0-21swapper/021:27:560
1618299332,28cyclictest0-21swapper/023:53:550
16182993316,5cyclictest3-21ksoftirqd/021:48:500
1618299331,4cyclictest81rcu_preempt23:22:120
1618299331,30cyclictest0-21swapper/000:19:150
1618299331,29cyclictest0-21swapper/000:43:150
1618299331,20cyclictest12616-21rm00:53:110
1618299331,20cyclictest12616-21rm00:53:100
16182993310,6cyclictest27861-21ssh00:00:300
153282331,28sleep015333-21irqstats20:45:200
318482321,4sleep131925-21latency_hist20:05:001
234802321,4sleep123493-21df_inode00:30:131
1618399325,4cyclictest81rcu_preempt21:15:391
1618399323,5cyclictest81rcu_preempt23:25:151
1618399321,5cyclictest81rcu_preempt20:39:011
1618399321,4cyclictest81rcu_preempt22:52:231
16182993225,5cyclictest0-21swapper/021:05:350
1618299322,19cyclictest0-21swapper/021:55:150
1618299322,14cyclictest20756-21munin-run21:40:010
1618299321,5cyclictest0-21swapper/023:59:160
1618299321,29cyclictest0-21swapper/023:42:360
64732311,4sleep125388-21kworker/1:222:31:071
1618399311,4cyclictest81rcu_preempt23:16:571
1618399311,4cyclictest81rcu_preempt22:46:351
1618399311,4cyclictest81rcu_preempt20:45:251
1618399311,4cyclictest81rcu_preempt20:09:291
1618399311,4cyclictest81rcu_preempt00:21:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional