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2026-08-20 - 20:17

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #9, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot4s (updated Thu Aug 20, 2026 12:59:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290929912141205,6cyclictest0-21swapper/107:25:061
290929911471123,18cyclictest6422-21copy07:45:381
290919911281104,21cyclictest0-21swapper/007:25:040
281642578531,31sleep10-21swapper/107:20:261
290022514417,30sleep00-21swapper/007:24:400
2493921040,7sleep00-21swapper/008:35:250
29091999875,20cyclictest0-21swapper/007:45:370
16232770,2sleep10-21swapper/111:50:311
314862381,4sleep131565-21df07:30:051
209952381,4sleep121004-21sh12:44:591
2909199379,12cyclictest26068-21netstat11:30:230
29091993712,13cyclictest30853-21runrttasks10:17:160
2909299358,6cyclictest249402sh08:35:261
29092993523,8cyclictest14871-21ls08:10:121
141822351,30sleep014186-21cron09:34:590
29092993410,10cyclictest122132sh09:29:001
29092993410,10cyclictest122132sh09:28:591
2909199347,3cyclictest0-21swapper/008:55:120
2909199345,5cyclictest81rcu_preempt10:35:000
2909199341,20cyclictest1399-21memory10:25:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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