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2026-10-22 - 03:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Thu Oct 22, 2026 00:53:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3811:21:255033
36,11:20:475032
38,11:20:475031
24,11:20:475030
011:20:475026
0,11:20:475025
0,11:20:475024
0,11:20:475023
0,11:20:475022
0,11:20:475021
0,11:20:475020
0,11:20:475019
0,11:20:475018
0,11:20:475017
0,11:20:475016
0,11:20:475015
0,11:20:475014
0,11:20:475013
0,11:20:475012
0,11:20:475011
0,11:20:475010
0,11:20:475009
0,11:20:475008
0,11:20:475007
0,11:20:475006
0,11:20:475005
0,11:20:475004
0,11:20:475003
0,11:20:475002
0,11:20:475001
0,11:20:475000
0,11:20:474999
0,11:20:474998
0,11:20:474997
0,11:20:474996
0,11:20:474995
0,11:20:474994
0,11:20:474993
0,11:20:474992
0,11:20:474991
0,11:20:474990
0,11:20:474989
0,11:20:474988
0,11:20:474987
0,11:20:474986
0,11:20:474985
0,11:20:474984
0,11:20:474983
0,11:20:474982
0,11:20:474981
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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