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2026-01-19 - 22:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Mon Jan 19, 2026 12:54:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3810:49:425033
36,10:49:045032
38,10:49:045031
24,10:49:045030
010:49:045026
0,10:49:045025
0,10:49:045024
0,10:49:045023
0,10:49:045022
0,10:49:045021
0,10:49:045020
0,10:49:045019
0,10:49:045018
0,10:49:045017
0,10:49:045016
0,10:49:045015
0,10:49:045014
0,10:49:045013
0,10:49:045012
0,10:49:045011
0,10:49:045010
0,10:49:045009
0,10:49:045008
0,10:49:045007
0,10:49:045006
0,10:49:045005
0,10:49:045004
0,10:49:045003
0,10:49:045002
0,10:49:045001
0,10:49:045000
0,10:49:044999
0,10:49:044998
0,10:49:044997
0,10:49:044996
0,10:49:044995
0,10:49:044994
0,10:49:044993
0,10:49:044992
0,10:49:044991
0,10:49:044990
0,10:49:044989
0,10:49:044988
0,10:49:044987
0,10:49:044986
0,10:49:044985
0,10:49:044984
0,10:49:044983
0,10:49:044982
0,10:49:044981
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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