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2026-03-13 - 18:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackaslot0.osadl.org (updated Fri Mar 13, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3111521100,0sleep20-21swapper/211:05:422
283721100,0sleep32805-21sshd11:00:223
205612710,1sleep220554-21sshd09:27:542
282442620,1sleep00-21swapper/012:34:140
9992610,0sleep10-21swapper/111:57:251
173702580,1sleep30-21swapper/311:18:533
192262570,0sleep20-21swapper/209:16:202
54202560,0sleep10-21swapper/109:23:451
269662560,0sleep226969-21id11:51:052
210312560,0sleep10-21swapper/112:04:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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