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2025-11-27 - 21:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackaslot0.osadl.org (updated Thu Nov 27, 2025 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1564121240,0sleep015624-21sshd10:15:350
74822800,0sleep37472-21sshd10:19:063
2764926427,19sleep10-21swapper/107:07:061
4832570,1sleep020912-21diskmemload12:35:520
201142570,0sleep120912-21diskmemload09:46:521
48932550,0sleep20-21swapper/210:55:592
246482540,1sleep21819-21runrttasks10:54:152
30442530,1sleep32814199cyclictest12:08:473
2756125330,9sleep20-21swapper/207:05:592
81962520,0sleep30-21swapper/309:33:323
79022510,0sleep00-21swapper/010:01:530
286272510,0sleep30-21swapper/310:42:183
2766525132,15sleep30-21swapper/307:07:163
2752925128,19sleep00-21swapper/007:05:330
236202510,0sleep20-21swapper/210:16:362
259552500,1sleep12813999cyclictest09:10:251
58092490,0sleep20-21swapper/212:36:262
87812470,0sleep10-21swapper/109:41:311
30242450,0sleep03022-21sshd11:28:580
185162450,0sleep00-21swapper/011:38:470
257422410,1sleep20-21swapper/212:31:492
151662380,0sleep315168-21id11:38:223
2813899240,23cyclictest0-21swapper/007:25:160
2814099220,21cyclictest0-21swapper/209:39:462
2814099220,21cyclictest0-21swapper/209:25:192
2813899220,21cyclictest0-21swapper/011:51:150
189882220,1sleep00-21swapper/009:50:470
172652220,0sleep00-21swapper/010:36:370
28141992119,1cyclictest0-21swapper/312:19:403
2814099210,20cyclictest0-21swapper/208:47:152
2814099210,20cyclictest0-21swapper/208:33:162
2814099210,20cyclictest0-21swapper/208:25:162
2813999211,19cyclictest0-21swapper/109:27:151
2813999210,20cyclictest0-21swapper/108:35:151
28138992119,1cyclictest7791-21sshd10:56:230
2813899210,20cyclictest0-21swapper/011:55:200
2813899210,20cyclictest0-21swapper/011:15:170
2813899210,20cyclictest0-21swapper/011:01:310
168482210,0sleep20-21swapper/211:26:322
28140992018,1cyclictest0-21swapper/211:02:012
28140992018,1cyclictest0-21swapper/210:07:572
2814099200,19cyclictest0-21swapper/211:11:012
2814099200,19cyclictest0-21swapper/207:52:152
2814099200,19cyclictest0-21swapper/207:28:462
28139992018,1cyclictest1664-21sshd09:38:011
2813999200,20cyclictest0-21swapper/110:45:011
2813999200,19cyclictest0-21swapper/111:49:161
2813899201,19cyclictest0-21swapper/008:36:150
2813899200,19cyclictest0-21swapper/009:11:310
271052200,1sleep227066-21sshd10:13:042
209422200,1sleep00-21swapper/009:26:470
2814099191,17cyclictest0-21swapper/209:10:162
2814099191,17cyclictest0-21swapper/208:20:452
2814099190,18cyclictest0-21swapper/210:39:162
2814099190,18cyclictest0-21swapper/210:24:162
2814099190,18cyclictest0-21swapper/207:34:162
2814099190,18cyclictest0-21swapper/207:23:162
28139991917,1cyclictest1664-21sshd11:22:521
2813999191,18cyclictest0-21swapper/110:27:001
2813899191,17cyclictest0-21swapper/009:41:000
2814099180,17cyclictest0-21swapper/210:30:112
2814099180,17cyclictest0-21swapper/209:57:462
2814099180,17cyclictest0-21swapper/209:43:162
2814099180,17cyclictest0-21swapper/209:34:462
2814099180,17cyclictest0-21swapper/208:19:152
2814099180,17cyclictest0-21swapper/207:37:002
28139991816,1cyclictest1664-21sshd10:55:171
2813999180,17cyclictest0-21swapper/111:00:161
268142180,0sleep30-21swapper/310:37:573
2814099170,16cyclictest0-21swapper/212:27:312
2814099170,16cyclictest0-21swapper/212:27:312
2814099170,16cyclictest0-21swapper/211:18:012
2814099170,16cyclictest0-21swapper/209:09:002
2814099170,16cyclictest0-21swapper/208:51:152
2814099170,16cyclictest0-21swapper/207:59:152
2813899170,16cyclictest8948-21sshd09:16:410
28140991613,2cyclictest29256-21sshd09:48:012
2814099160,15cyclictest0-21swapper/212:12:162
2814099160,15cyclictest0-21swapper/212:02:462
2814099160,15cyclictest0-21swapper/210:04:152
2814099160,15cyclictest0-21swapper/208:37:462
2814099160,15cyclictest0-21swapper/208:05:102
28139991615,1cyclictest1664-21sshd10:50:401
28139991615,1cyclictest1664-21sshd10:11:281
2813999160,16cyclictest0-21swapper/112:25:171
2813999160,16cyclictest0-21swapper/112:25:161
2813999160,15cyclictest0-21swapper/112:34:311
2813999160,15cyclictest0-21swapper/107:35:151
2813999160,14cyclictest0-21swapper/112:38:311
28138991612,1cyclictest29653-21sshd11:07:530
28138991611,3cyclictest0-21swapper/011:31:390
2813899160,15cyclictest29644-21sshd10:42:240
2813899160,15cyclictest0-21swapper/011:47:160
2813899160,15cyclictest0-21swapper/011:10:090
2813899160,15cyclictest0-21swapper/010:23:460
2813899160,15cyclictest0-21swapper/010:06:110
2813899160,15cyclictest0-21swapper/008:55:170
85292150,1sleep30-21swapper/311:33:383
2814199159,1cyclictest0-21swapper/310:48:233
2814199150,12cyclictest0-21swapper/309:16:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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