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2025-12-01 - 23:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Mon Dec 01, 2025 12:44:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77502600,1sleep37724-21sshd11:27:593
290162590,1sleep00-21swapper/011:34:370
261822590,0sleep30-21swapper/310:45:213
2373125624,28sleep30-21swapper/307:06:473
220922560,1sleep11578-21nfsd09:52:311
2365125431,19sleep20-21swapper/207:05:462
2197725417,19sleep00-21swapper/007:05:170
92152530,0sleep10-21swapper/109:22:191
317992530,1sleep317034-21diskmemload10:25:583
229832530,1sleep00-21swapper/009:52:370
291742520,1sleep129168-21sshd11:34:381
2394325229,19sleep10-21swapper/107:09:301
105812520,0sleep30-21swapper/310:59:553
47642500,0sleep10-21swapper/111:27:371
309682500,0sleep30-21swapper/310:14:093
319582490,0sleep00-21swapper/009:42:010
298132490,0sleep30-21swapper/309:45:363
17242490,1sleep01719-21sshd11:47:110
177732480,1sleep30-21swapper/310:16:253
109112480,1sleep310867-21sshd12:26:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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