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2026-03-19 - 17:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Mar 19, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231892950,0sleep010-21rcuc/010:48:120
196082950,1sleep119-21rcuc/112:28:501
259092920,0sleep00-21swapper/011:51:510
130262600,0sleep113025-21sshd11:59:251
121212600,0sleep20-21swapper/210:12:412
84182590,1sleep119-21rcuc/111:07:051
63752580,0sleep337-21rcuc/311:41:283
269772570,1sleep10-21swapper/110:39:561
196462570,0sleep319619-21sshd10:36:173
11072570,1sleep30-21swapper/310:17:273
65502560,0sleep36535-21sshd11:24:173
292212530,0sleep30-21swapper/311:08:583
270372530,0sleep019606-21diskmemload09:13:290
140212530,1sleep014019-21sshd11:30:350
76032520,0sleep08-21rcu_preempt10:29:330
298652520,2sleep10-21swapper/112:21:011
291812520,1sleep228-21rcuc/211:55:062
208912520,0sleep228-21rcuc/212:17:212
146052520,1sleep30-21swapper/310:10:053
133162520,0sleep20-21swapper/211:19:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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