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2025-11-20 - 19:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Nov 20, 2025 12:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103262920,0sleep20-21swapper/209:16:072
32332610,0sleep00-21swapper/011:19:110
89742590,0sleep337-21rcuc/312:22:433
316872570,0sleep10-21swapper/112:32:191
227625735,18sleep30-21swapper/307:05:393
231325634,19sleep10-21swapper/107:06:061
40412550,0sleep00-21swapper/009:44:370
204192550,0sleep120398-21sshd10:48:191
182132540,0sleep00-21swapper/012:27:250
238825330,19sleep20-21swapper/207:07:022
226825325,9sleep00-21swapper/007:05:320
104292530,0sleep01819-21runrttasks10:13:530
77002510,1sleep30-21swapper/311:47:583
270932510,1sleep31819-21runrttasks11:54:283
236892510,0sleep00-21swapper/010:15:290
15372510,1sleep31501-21sshd11:58:593
320802500,0sleep10-21swapper/112:35:441
31802500,0sleep10-21swapper/112:25:421
306402480,0sleep20-21swapper/211:10:112
254732480,0sleep20-21swapper/212:20:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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