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2026-05-19 - 09:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue May 19, 2026 00:44:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12182960,2sleep31861499cyclictest00:05:443
12182960,2sleep31861499cyclictest00:05:443
260852900,0sleep30-21swapper/300:16:383
125272900,2sleep01861199cyclictest21:57:250
266062590,1sleep08-21rcu_preempt23:47:540
40842570,0sleep30-21swapper/321:36:373
324932570,0sleep10-21swapper/121:50:331
111202570,0sleep30-21swapper/323:37:523
38082560,2sleep1201ktimersoftd/100:14:441
158692560,1sleep315857-21sshd22:17:523
40452540,0sleep31734-21runrttasks00:32:003
273282540,0sleep20-21swapper/221:12:552
181802540,0sleep20-21swapper/222:09:292
1782425432,18sleep00-21swapper/019:07:220
207912530,1sleep337-21rcuc/300:24:553
86362520,1sleep325722-21diskmemload00:29:363
297082520,1sleep20-21swapper/223:33:472
246142520,0sleep30-21swapper/322:21:293
152872520,0sleep00-21swapper/000:04:130
316072510,1sleep20-21swapper/223:56:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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