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2026-05-11 - 11:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Mon May 11, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
108382940,0sleep10-21swapper/100:04:101
306272860,0sleep20-21swapper/221:23:452
318062650,0sleep31734-21runrttasks22:40:313
268112640,0sleep20-21swapper/222:11:442
223842610,0sleep10-21swapper/121:11:381
6802600,0sleep20-21swapper/223:43:152
251862600,1sleep337-21rcuc/323:16:563
272472590,0sleep21734-21runrttasks22:06:032
21762590,0sleep20-21swapper/200:03:222
181022590,1sleep00-21swapper/021:14:090
61962570,0sleep00-21swapper/022:07:060
274562570,0sleep30-21swapper/322:28:533
158232570,0sleep10-21swapper/122:02:151
282032560,1sleep02481-21diskmemload00:20:000
109692560,0sleep30-21swapper/321:39:053
62302550,0sleep20-21swapper/222:18:292
291472540,0sleep329135-21sshd00:25:393
190182540,0sleep318999-21sshd00:13:253
314602530,1sleep32481-21diskmemload21:15:173
2725325326,8sleep30-21swapper/319:08:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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