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2026-03-31 - 17:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue Mar 31, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2906521100,0sleep029061-21sshd11:46:010
65642620,0sleep26563-21sshd10:10:242
69122610,0sleep30-21swapper/309:19:333
1883026125,18sleep00-21swapper/007:09:050
37222600,0sleep3381ktimersoftd/311:52:213
1880026023,33sleep30-21swapper/307:08:563
201762560,0sleep220162-21sshd09:15:032
319772550,1sleep00-21swapper/010:09:540
280092550,1sleep328008-21sshd10:15:143
286392540,0sleep21734-21runrttasks10:09:362
1891625428,9sleep10-21swapper/107:09:301
187812540,0sleep10-21swapper/109:23:241
187812540,0sleep10-21swapper/109:23:231
102122540,0sleep20-21swapper/212:07:062
290882510,0sleep20-21swapper/209:41:122
1815325128,8sleep20-21swapper/207:05:432
7642500,0sleep20-21swapper/211:29:292
117682500,0sleep20-21swapper/211:13:182
74682490,0sleep20-21swapper/209:33:422
29032490,0sleep00-21swapper/009:58:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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