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2026-07-25 - 02:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Jul 24, 2026 12:44:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
257602970,1sleep337-21rcuc/312:12:143
68982880,1sleep26896-21sshd11:30:382
181462690,0sleep10-21swapper/111:28:531
60582680,0sleep06040-21sshd12:33:180
97412660,1sleep09708-21sshd10:05:350
60112660,0sleep10-21swapper/110:11:001
9792620,1sleep3956-21sshd11:24:343
189232620,0sleep00-21swapper/009:23:480
308722610,1sleep10-21swapper/111:07:141
1306226124,18sleep00-21swapper/007:05:010
139862590,1sleep00-21swapper/009:26:080
119942590,1sleep211982-21sshd12:39:332
72692580,0sleep2291ktimersoftd/209:11:202
310092570,0sleep10-21swapper/110:01:471
249962570,1sleep324994-21sshd11:49:273
84452550,1sleep38431-21sshd10:59:393
33042550,0sleep00-21swapper/009:33:490
274232540,0sleep027421-21cp12:12:230
18252510,0sleep00-21swapper/011:04:440
179102500,1sleep00-21swapper/009:52:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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