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2026-09-05 - 13:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Sep 05, 2026 00:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62922980,1sleep06282-21sshd23:24:240
190312780,1sleep219012-21sshd21:41:132
220992750,0sleep20-21swapper/222:07:382
227612690,0sleep00-21swapper/022:30:510
174822660,0sleep20-21swapper/200:29:072
3101126327,18sleep30-21swapper/319:07:513
139692620,0sleep20-21swapper/222:50:212
289442610,6sleep339-21ksoftirqd/321:56:373
243752590,0sleep00-21swapper/000:29:450
42502570,0sleep30-21swapper/321:37:023
247142570,1sleep10-21swapper/121:12:521
194792570,0sleep324131-21diskmemload00:32:083
93132540,1sleep29312-21sshd22:41:142
104842540,0sleep30-21swapper/322:26:533
62712530,0sleep30-21swapper/323:30:103
3109025331,18sleep20-21swapper/219:08:502
3080925327,22sleep10-21swapper/119:05:261
2905625227,20sleep00-21swapper/019:05:130
269652520,0sleep00-21swapper/000:21:120
246152520,0sleep10-21swapper/100:12:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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