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2026-04-08 - 13:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Apr 08, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304422850,0sleep10-21swapper/122:34:021
249152830,0sleep224912-21cp21:44:452
249152830,0sleep224912-21cp21:44:452
112172640,0sleep111197-21sshd00:33:131
95852610,0sleep30-21swapper/300:38:523
220822600,1sleep322081-21bash22:50:273
179512600,1sleep00-21swapper/000:10:410
81292590,1sleep20-21swapper/221:54:462
81292590,1sleep20-21swapper/221:54:462
9752570,1sleep321547-21diskmemload21:28:143
9752570,1sleep321547-21diskmemload21:28:143
298512560,0sleep00-21swapper/021:53:470
298512560,0sleep00-21swapper/021:53:470
190632560,1sleep00-21swapper/023:10:200
191692550,0sleep00-21swapper/000:05:080
191692550,0sleep00-21swapper/000:05:080
200942530,0sleep10-21swapper/122:58:591
199512520,1sleep319948-21sshd22:10:093
1369725222,4sleep20-21swapper/219:07:372
325312510,0sleep20-21swapper/222:19:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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