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2026-07-22 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Jul 22, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1221521020,2sleep11734-21runrttasks19:08:291
82062850,1sleep31734-21runrttasks23:36:073
90162600,0sleep30-21swapper/322:50:033
253172600,0sleep20-21swapper/222:28:242
76672590,0sleep30-21swapper/322:29:443
251672590,0sleep20-21swapper/223:55:092
168702590,0sleep20-21swapper/222:50:392
51632570,0sleep00-21swapper/021:14:250
115672570,0sleep00-21swapper/023:24:590
269022560,1sleep226891-21sshd23:52:202
195242560,0sleep30-21swapper/322:16:153
152682560,0sleep30-21swapper/321:52:463
281332550,0sleep30-21swapper/323:03:173
164282550,0sleep216424-21sshd23:16:402
316492540,0sleep30-21swapper/322:43:223
295202540,0sleep30-21swapper/323:12:033
274262540,6sleep121-21ksoftirqd/122:19:571
21192540,0sleep20-21swapper/221:42:562
1225225425,25sleep00-21swapper/019:08:410
44972530,1sleep228-21rcuc/221:54:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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