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2026-08-21 - 06:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Aug 21, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
99512940,0sleep20-21swapper/222:56:352
151672890,0sleep00-21swapper/021:10:320
144232840,0sleep114409-21sshd22:22:251
198762620,0sleep319877-21sshd22:31:333
50772610,0sleep30-21swapper/322:56:083
120322610,0sleep10-21swapper/122:45:161
149282580,0sleep20-21swapper/200:00:302
1384625825,9sleep00-21swapper/019:05:250
31732560,1sleep33174-21bash23:24:573
242512560,0sleep10-21swapper/100:12:581
262732550,1sleep31866-21runrttasks22:09:043
221492550,1sleep222151-21bash21:54:222
169192550,0sleep20-21swapper/221:56:422
123302540,0sleep30-21swapper/323:51:373
78542530,1sleep10-21swapper/123:13:451
248292530,0sleep10-21swapper/123:38:201
24382530,0sleep00-21swapper/021:38:130
185112530,1sleep337-21rcuc/321:13:483
1435925331,18sleep20-21swapper/219:09:572
1410825229,19sleep10-21swapper/119:06:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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