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2026-07-09 - 20:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Jul 09, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1671221040,0sleep316713-21sshd11:52:423
3238621010,0sleep232384-21bash10:05:552
1695321010,1sleep216944-21bash09:24:572
91112940,1sleep09107-21sshd09:29:560
205922940,0sleep30-21swapper/310:30:283
229632930,1sleep10-21swapper/112:16:011
326442920,3sleep332625-21sshd11:31:193
190062670,1sleep319007-21sshd11:58:393
190062670,1sleep319007-21sshd11:58:393
3202426025,18sleep10-21swapper/107:07:591
225322590,0sleep122520-21sshd12:35:551
210162590,0sleep20-21swapper/211:58:512
210162590,0sleep20-21swapper/211:58:502
145202580,1sleep014521-21sshd11:38:170
217692560,0sleep30-21swapper/311:24:463
176232560,1sleep10-21swapper/109:53:211
140512560,0sleep337-21rcuc/312:00:593
132092560,1sleep228-21rcuc/210:58:202
305002550,1sleep130487-21sshd10:31:231
249602550,0sleep324957-21sshd09:22:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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