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2025-09-18 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Sep 17, 2025 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
457021130,0sleep24497-21sshd10:27:032
209121050,0sleep32079-21sshd11:56:143
42952960,1sleep013377-21diskmemload10:56:060
195392880,0sleep219540-21sshd09:36:382
172672880,0sleep30-21swapper/310:49:443
174642660,0sleep10-21swapper/111:06:561
68932640,1sleep06874-21sshd09:19:190
266172620,1sleep30-21swapper/311:04:543
154592620,1sleep015439-21sshd10:19:080
82902590,2sleep12066399cyclictest12:10:461
323782580,0sleep20-21swapper/212:38:322
68882560,0sleep00-21swapper/010:33:180
207862560,0sleep00-21swapper/010:46:360
125332560,0sleep212462-21sshd10:49:062
245662550,1sleep024560-21sshd11:28:220
117212550,0sleep20-21swapper/211:57:052
29792540,0sleep10-21swapper/109:29:091
178752530,0sleep117878-21id11:21:541
12102530,0sleep21211-21sshd11:14:262
72142520,0sleep10-21swapper/110:00:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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