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2026-03-15 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun Mar 15, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232972970,0sleep023273-21sshd10:26:350
172632970,1sleep217244-21sshd12:23:352
150212950,0sleep014983-21sshd11:20:200
150212950,0sleep014983-21sshd11:20:200
250172900,0sleep30-21swapper/312:01:163
200262650,0sleep00-21swapper/010:37:490
208182610,0sleep230-21ksoftirqd/211:20:492
208182610,0sleep230-21ksoftirqd/211:20:492
2948026024,32sleep10-21swapper/107:06:161
126492600,1sleep00-21swapper/009:22:070
185882580,1sleep30-21swapper/312:32:183
302512570,5sleep03-21ksoftirqd/011:58:580
185562570,0sleep00-21swapper/012:06:270
234582560,1sleep123436-21sshd09:46:091
10272560,0sleep00-21swapper/011:50:320
307382550,1sleep05208-21diskmemload11:27:290
2751725522,4sleep30-21swapper/307:05:093
296352540,0sleep10-21swapper/110:21:221
294462530,0sleep10-21swapper/109:17:531
188792530,0sleep05208-21diskmemload12:15:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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