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2026-01-05 - 04:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Mon Jan 05, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189282850,0sleep10-21swapper/100:12:091
221112610,1sleep322113-21sshd00:07:143
183672600,0sleep30-21swapper/323:28:443
135252570,1sleep20-21swapper/221:39:102
187702550,1sleep10-21swapper/122:12:231
3055725432,18sleep20-21swapper/219:05:342
3106125327,9sleep30-21swapper/319:09:093
3101725325,9sleep10-21swapper/119:08:511
130232530,2sleep337-21rcuc/321:55:143
3093425028,18sleep00-21swapper/019:08:140
40802490,1sleep21734-21runrttasks22:31:392
40802490,1sleep21734-21runrttasks22:31:392
296292490,1sleep30-21swapper/321:47:103
50242480,0sleep00-21swapper/022:37:180
78842440,0sleep00-21swapper/021:16:370
258592420,0sleep00-21swapper/000:29:550
96662410,0sleep20-21swapper/222:16:122
269082370,0sleep226905-21cp22:40:512
106452370,1sleep23143999cyclictest00:16:102
3143099171,1cyclictest0-21swapper/022:43:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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