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2026-04-19 - 20:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun Apr 19, 2026 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218852920,0sleep02606499cyclictest10:18:040
218852920,0sleep02606499cyclictest10:18:040
25702810,0sleep1717-21diskmemload10:22:061
25702810,0sleep1717-21diskmemload10:22:061
2506626426,19sleep30-21swapper/307:06:213
73402610,0sleep20-21swapper/209:13:232
2543025923,9sleep00-21swapper/007:08:100
173202570,1sleep30-21swapper/310:14:503
105682570,1sleep310544-21sshd12:32:563
126862560,0sleep112603-21sshd09:25:211
141612550,0sleep30-21swapper/311:38:123
103862550,0sleep20-21swapper/211:43:392
319752540,0sleep18-21rcu_preempt10:44:581
223002540,0sleep30-21swapper/310:58:293
100262540,2sleep12606599cyclictest12:06:461
64602530,0sleep00-21swapper/011:02:520
2308225327,11sleep20-21swapper/207:05:072
251642520,0sleep230-21ksoftirqd/211:30:252
2496525216,32sleep10-21swapper/107:05:501
200782520,0sleep20-21swapper/211:50:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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