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2025-05-03 - 01:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri May 02, 2025 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1241021100,1sleep112406-21rm10:24:381
284122870,0sleep20-21swapper/211:37:232
1650126927,38sleep10-21swapper/107:05:001
82112660,1sleep18191-21sshd12:02:541
3092660,1sleep132764-21sshd11:57:091
314092610,0sleep00-21swapper/009:38:100
256672610,1sleep31909999cyclictest11:10:083
225812580,0sleep10-21swapper/112:24:371
84952570,1sleep31722-21runrttasks12:36:133
280382570,0sleep20-21swapper/211:13:402
3732550,0sleep1348-21sshd09:48:181
305232540,1sleep20-21swapper/212:22:382
266282540,1sleep326583-21sshd11:40:133
249402540,1sleep21507-21nfsd10:06:502
209012540,1sleep11722-21runrttasks09:17:121
149592540,0sleep30-21swapper/310:46:443
314202530,1sleep10-21swapper/111:54:331
306502520,1sleep330642-21sshd11:28:473
50352510,0sleep10-21swapper/112:33:271
45832510,0sleep30-21swapper/310:55:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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