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2026-04-10 - 16:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Apr 10, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41562950,0sleep30-21swapper/311:32:113
228452650,2sleep00-21swapper/012:20:030
172352630,0sleep20-21swapper/211:01:372
1725126125,18sleep00-21swapper/007:09:460
1699326024,9sleep10-21swapper/107:08:321
126202590,1sleep30-21swapper/310:12:103
18892580,1sleep21890-21sshd10:34:212
218602570,1sleep121861-21sshd09:38:261
264732560,0sleep00-21swapper/011:19:500
294122550,0sleep10-21swapper/111:45:551
249702550,1sleep124968-21sshd10:27:431
81562540,0sleep20-21swapper/209:48:452
201242540,0sleep10-21swapper/111:19:151
100222540,3sleep228-21rcuc/210:26:202
89532530,0sleep28934-21sshd09:22:532
301492530,1sleep01734-21runrttasks12:03:210
217782530,0sleep30-21swapper/310:44:473
11872530,0sleep3381ktimersoftd/311:52:063
44312520,0sleep10-21swapper/111:03:241
188012520,0sleep10-21swapper/111:50:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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