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2026-07-28 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue Jul 28, 2026 00:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167442800,2sleep316746-21nfsd419:05:283
250262620,1sleep20-21swapper/223:03:252
249882620,0sleep10-21swapper/121:42:081
193912600,1sleep319385-21sshd22:55:213
233912570,0sleep00-21swapper/022:48:290
97812550,1sleep20-21swapper/222:32:082
179862550,0sleep00-21swapper/022:33:060
206872540,1sleep320667-21sshd21:12:083
78792530,0sleep30-21swapper/300:22:433
1735825327,8sleep00-21swapper/019:05:420
37172520,1sleep13694-21sshd21:28:421
264602520,1sleep326458-21sshd23:29:273
216372520,0sleep30-21swapper/321:19:413
304102510,0sleep20-21swapper/219:25:182
290482510,0sleep20-21swapper/223:22:162
1743925127,20sleep20-21swapper/219:06:002
131772510,0sleep00-21swapper/000:08:340
109992510,1sleep10-21swapper/122:28:391
108492510,1sleep11734-21runrttasks23:09:131
88032500,0sleep0596-21diskmemload21:18:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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