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2026-07-04 - 22:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Jul 04, 2026 12:44:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87982890,0sleep00-21swapper/012:28:290
319882660,1sleep231987-21bash09:27:502
251592650,0sleep225157-21sshd11:00:022
287532590,0sleep20-21swapper/211:17:442
1776925923,9sleep30-21swapper/307:08:253
209282560,1sleep320914-21sshd10:10:183
50182550,0sleep15015-21sshd10:58:111
45702550,0sleep30-21swapper/312:22:153
263042550,1sleep30-21swapper/309:18:423
141982550,0sleep30-21swapper/310:15:273
239432540,0sleep10-21swapper/109:24:171
211032540,1sleep30-21swapper/311:02:313
95122530,1sleep09496-21sshd09:49:030
62392530,1sleep30-21swapper/312:05:053
23502530,1sleep22348-21sshd12:30:442
12042530,0sleep218326-21cyclictest09:10:342
88152520,0sleep3381ktimersoftd/310:23:483
88152520,0sleep3381ktimersoftd/310:23:483
33602520,0sleep20-21swapper/212:27:592
258492520,1sleep325847-21bash11:08:483
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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