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2026-05-31 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun May 31, 2026 00:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2049021080,0sleep20-21swapper/222:40:232
49212720,2sleep20-21swapper/222:10:212
7082630,0sleep3693-21sshd00:30:343
2406626325,19sleep10-21swapper/119:06:181
270852620,0sleep30-21swapper/323:01:033
107182620,0sleep20-21swapper/221:50:472
185192590,0sleep218515-21sshd23:34:472
191302580,0sleep10-21swapper/123:43:241
130592580,0sleep00-21swapper/000:00:050
127382580,0sleep212737-21sshd23:54:182
310652570,0sleep10-21swapper/123:10:061
227782560,0sleep10-21swapper/121:20:241
124982560,1sleep312497-21sshd22:34:033
318232550,0sleep10-21swapper/100:19:011
27342550,0sleep12733-21sshd22:35:571
235902550,0sleep010-21rcuc/022:29:190
285872540,1sleep032172-21diskmemload21:49:360
258922540,1sleep228-21rcuc/223:29:422
216262540,0sleep10-21swapper/100:38:161
121712530,0sleep10-21swapper/122:34:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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