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2026-09-20 - 20:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun Sep 20, 2026 12:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100152650,1sleep01866-21runrttasks12:04:230
100152650,1sleep01866-21runrttasks12:04:230
298322590,0sleep20-21swapper/211:49:582
23572570,0sleep32335-21sshd11:14:223
241882560,1sleep10-21swapper/109:15:221
193422560,0sleep119339-21sshd11:06:111
46692550,1sleep24667-21sshd12:33:252
268752540,1sleep2911599cyclictest09:38:342
195482540,1sleep00-21swapper/010:04:000
882225328,8sleep10-21swapper/107:09:341
874325327,22sleep00-21swapper/007:08:410
32492530,1sleep21866-21runrttasks12:36:302
870725227,22sleep30-21swapper/307:08:163
307432520,0sleep20-21swapper/209:25:482
307432520,0sleep20-21swapper/209:25:482
860725129,18sleep20-21swapper/207:06:592
61352510,0sleep06136-21sshd10:25:310
27172510,1sleep28-21rcu_preempt11:17:372
125762510,0sleep30-21swapper/310:00:033
292052500,0sleep20-21swapper/209:58:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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