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2026-04-19 - 13:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun Apr 19, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1389721050,1sleep313892-21bash21:27:183
307922980,0sleep130791-21sshd22:32:101
199562980,0sleep00-21swapper/023:20:140
51202670,0sleep20-21swapper/221:23:412
277272660,0sleep10-21swapper/122:40:281
238432640,1sleep223834-21sshd23:40:392
523026224,19sleep30-21swapper/319:07:203
181282600,0sleep20-21swapper/221:45:012
65292590,1sleep16530-21bash23:53:361
293742590,1sleep029355-21sshd00:24:200
256102590,1sleep325592-21sshd23:26:263
201262580,1sleep337-21rcuc/321:22:053
161142580,0sleep20-21swapper/221:39:042
139722580,0sleep20-21swapper/222:10:282
130602580,1sleep313058-21sshd23:16:403
184482570,0sleep30-21swapper/321:39:163
80302560,0sleep20-21swapper/221:52:412
137472560,1sleep313723-21sshd23:51:183
317772550,1sleep031773-21sshd00:01:320
137242550,0sleep10-21swapper/121:38:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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