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2026-05-13 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed May 13, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37332940,0sleep10-21swapper/121:27:451
303552830,0sleep00-21swapper/021:44:180
83612700,0sleep30-21swapper/322:33:323
306202610,0sleep20-21swapper/223:23:522
1919126124,19sleep30-21swapper/319:07:203
102622600,0sleep327112-21diskmemload23:59:073
275912590,0sleep30-21swapper/321:26:583
275062580,0sleep227480-21sshd23:03:412
23062580,1sleep22304-21bash23:52:412
1894125824,18sleep20-21swapper/219:06:082
136122570,0sleep30-21swapper/323:53:423
289462560,1sleep227112-21diskmemload22:23:582
244422560,0sleep00-21swapper/023:48:570
230242560,0sleep119-21rcuc/123:37:261
126062550,0sleep10-21swapper/100:05:061
1918225425,9sleep00-21swapper/019:07:170
130782540,0sleep20-21swapper/223:16:352
130782540,0sleep20-21swapper/223:16:352
126832540,1sleep127112-21diskmemload21:48:241
66442530,0sleep10-21swapper/121:53:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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