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2026-08-12 - 06:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Aug 12, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
95172930,0sleep10-21swapper/123:07:441
2768426027,19sleep10-21swapper/119:09:461
2733626025,18sleep00-21swapper/019:05:250
209282590,0sleep10-21swapper/122:54:221
158622580,0sleep20-21swapper/223:19:582
145442580,0sleep20-21swapper/200:00:202
18182560,0sleep1201ktimersoftd/100:05:041
2685325518,33sleep30-21swapper/319:05:203
108472550,0sleep00-21swapper/023:51:220
37142540,0sleep10-21swapper/122:00:261
304532540,0sleep20-21swapper/200:22:072
2738425432,18sleep20-21swapper/219:05:592
203342540,1sleep120323-21sshd23:20:171
52092530,1sleep25211-21sshd22:15:132
36942530,1sleep33681-21sshd22:23:473
36942530,1sleep33681-21sshd22:23:473
32252530,1sleep220662-21diskmemload22:12:052
204132530,0sleep00-21swapper/021:21:260
68242520,1sleep01866-21runrttasks22:09:330
172652520,1sleep12795999cyclictest21:00:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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