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2026-05-25 - 11:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Mon May 25, 2026 00:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1032721130,0sleep210328-21id21:35:192
198432970,0sleep30-21swapper/323:32:063
149332910,2sleep11704399cyclictest00:31:011
1621226821,8sleep20-21swapper/219:07:072
252612600,0sleep30-21swapper/300:23:053
108602580,1sleep210842-21sshd22:34:462
51032560,0sleep30-21swapper/322:04:313
293002560,1sleep329281-21sshd00:38:193
1656425527,24sleep00-21swapper/019:08:540
7852540,0sleep01704299cyclictest00:11:520
189582540,0sleep10-21swapper/123:55:391
12092540,1sleep010-21rcuc/000:35:410
94502520,0sleep20-21swapper/200:39:302
54492520,1sleep15448-21sshd23:21:541
304642520,0sleep31734-21runrttasks23:41:563
278182520,1sleep041ktimersoftd/020:20:140
267832520,0sleep30-21swapper/323:47:323
220432510,0sleep30-21swapper/321:33:273
167892510,0sleep00-21swapper/000:07:230
1614625118,29sleep10-21swapper/119:06:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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