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2026-01-26 - 08:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Mon Jan 26, 2026 00:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
554026326,19sleep20-21swapper/219:09:522
70762610,0sleep228-21rcuc/200:22:012
70762610,0sleep228-21rcuc/200:22:012
192822610,2sleep00-21swapper/000:14:340
110082600,0sleep00-21swapper/022:07:170
209262590,1sleep213060-21diskmemload00:03:092
542225824,17sleep30-21swapper/319:09:173
165182580,2sleep3583099cyclictest00:28:393
69822570,0sleep00-21swapper/022:12:420
15032560,0sleep10-21swapper/122:09:231
53002550,0sleep10-21swapper/123:47:231
118582550,1sleep010-21rcuc/022:04:330
30452540,0sleep00-21swapper/000:18:500
148562540,1sleep1489-21jbd2/dm-0-822:16:161
543925329,20sleep00-21swapper/019:09:220
295432530,0sleep00-21swapper/000:35:280
193232530,0sleep019321-21sshd00:00:110
175862530,1sleep228-21rcuc/200:11:262
156932530,2sleep010-21rcuc/021:21:350
152382530,1sleep30-21swapper/322:47:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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