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2026-03-11 - 08:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Mar 11, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176421160,0sleep01757-21bash21:13:290
2516421000,0sleep20-21swapper/221:15:272
27842980,2sleep31939499cyclictest22:22:443
323402950,1sleep337-21rcuc/300:21:023
321372820,2sleep01939099cyclictest21:27:390
190032820,0sleep00-21swapper/000:16:590
117652660,0sleep211767-21sshd21:31:352
117652660,0sleep211767-21sshd21:31:352
13272640,1sleep00-21swapper/022:02:210
1844926125,18sleep00-21swapper/019:06:340
176182590,0sleep317600-21sshd23:50:463
57352580,1sleep119-21rcuc/122:20:091
271802570,1sleep127178-21ls22:10:231
226822570,0sleep00-21swapper/023:07:520
16242560,1sleep010-21rcuc/023:40:370
226632550,8sleep10-21swapper/122:04:181
95882530,0sleep00-21swapper/023:58:490
39592530,0sleep30-21swapper/300:30:123
256932530,0sleep00-21swapper/023:19:460
1855625326,9sleep10-21swapper/119:07:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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