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2026-04-15 - 18:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Apr 15, 2026 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65322950,0sleep10-21swapper/112:23:501
80722880,0sleep38057-21sshd11:04:363
77342790,0sleep20-21swapper/210:32:172
2173326325,19sleep30-21swapper/307:06:383
23412620,0sleep10-21swapper/112:08:431
2100026125,19sleep20-21swapper/207:05:202
78882600,0sleep20-21swapper/210:20:312
2049726022,33sleep10-21swapper/107:05:151
259172590,1sleep025912-21sshd09:23:590
213912590,1sleep20-21swapper/209:17:492
162322580,0sleep30-21swapper/312:15:473
43322570,1sleep11509-21nfsd11:30:331
317862570,0sleep231769-21sshd09:33:082
297662570,1sleep029760-21sshd12:20:050
22962560,1sleep32279-21sshd10:14:153
287372550,3sleep328715-21sshd09:44:313
234022530,1sleep10-21swapper/111:47:041
79892520,0sleep27987-21sshd09:22:222
32672520,0sleep2291ktimersoftd/209:10:242
307162520,0sleep20-21swapper/210:40:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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