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2026-06-03 - 12:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Jun 03, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
551021070,0sleep25511-21sshd22:00:542
124172940,0sleep00-21swapper/021:27:150
738426324,10sleep00-21swapper/019:07:330
206852630,1sleep01734-21runrttasks22:42:310
756626125,19sleep30-21swapper/319:08:293
264112590,1sleep226406-21sshd22:25:452
161122590,0sleep30-21swapper/323:28:053
63872580,0sleep30-21swapper/322:46:593
184462570,0sleep20-21swapper/223:36:532
190712550,1sleep019074-21sshd23:54:180
186882550,1sleep018662-21sshd21:36:210
186882550,1sleep018662-21sshd21:36:210
184932550,1sleep31734-21runrttasks00:37:203
301352540,0sleep20-21swapper/221:14:342
17352540,1sleep21734-21runrttasks00:27:132
172042540,0sleep210007-21diskmemload00:11:192
60362530,0sleep041ktimersoftd/023:04:100
203692530,1sleep00-21swapper/000:00:110
37512520,0sleep13742-21sshd23:41:211
114572520,0sleep20-21swapper/223:01:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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