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2026-05-14 - 04:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu May 14, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2110721010,3sleep3115650irq/25-eth023:31:263
65352940,0sleep16534-21sshd00:27:371
66672890,1sleep06668-21bash23:24:260
149472850,0sleep20-21swapper/200:16:532
10292850,1sleep21028-21sshd21:28:452
184262840,1sleep318425-21sshd23:48:293
256932650,13sleep1115650irq/25-eth023:34:491
21612620,2sleep1836099cyclictest23:58:331
111512620,1sleep011152-21sshd23:07:200
736426024,18sleep00-21swapper/019:06:210
229272590,0sleep30-21swapper/322:51:003
722625827,27sleep30-21swapper/319:05:403
68112560,0sleep20-21swapper/222:12:162
55542560,0sleep05529-21sshd00:21:470
96262550,1sleep215458-21diskmemload00:04:592
242412550,0sleep10-21swapper/123:02:441
240162550,1sleep124015-21sshd22:33:551
191202550,1sleep319085-21sshd21:30:183
269522540,1sleep026938-21sshd00:32:170
274572530,1sleep027458-21sshd22:51:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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