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2026-05-14 - 21:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu May 14, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2648421020,0sleep113013-21diskmemload10:28:271
85922870,0sleep10-21swapper/111:21:151
227012820,1sleep00-21swapper/009:25:070
218662660,0sleep121865-21bash10:45:131
519825932,9sleep00-21swapper/007:07:460
94392580,0sleep00-21swapper/011:09:560
201482580,1sleep220136-21sshd10:16:212
122742580,0sleep312269-21rm10:41:263
322432570,1sleep132241-21bash12:32:261
149472560,1sleep30-21swapper/311:59:153
169302550,0sleep016927-21sshd10:41:510
175432540,0sleep20-21swapper/212:22:292
174752540,1sleep30-21swapper/311:33:343
10232540,0sleep30-21swapper/310:17:343
85232520,1sleep28508-21sshd11:41:182
326602520,0sleep30-21swapper/312:06:323
246432520,2sleep324639-21sshd12:00:073
236272520,0sleep10-21swapper/110:56:471
179392520,0sleep30-21swapper/309:18:573
16172520,1sleep00-21swapper/011:40:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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