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2025-12-23 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue Dec 23, 2025 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121682590,1sleep31734-21runrttasks08:10:223
318442560,0sleep10-21swapper/112:36:121
286262560,0sleep00-21swapper/010:12:010
951125533,18sleep20-21swapper/207:07:502
948925426,9sleep00-21swapper/007:07:400
715025431,19sleep10-21swapper/107:05:011
954925331,19sleep30-21swapper/307:08:073
266442530,0sleep10-21swapper/109:24:101
45172520,0sleep10-21swapper/111:40:201
35622510,0sleep20-21swapper/210:42:472
267102510,0sleep30-21swapper/310:11:243
105852500,1sleep31734-21runrttasks12:30:133
54842490,0sleep30-21swapper/312:38:103
254732470,0sleep19962-21diskmemload09:42:381
324412450,0sleep31734-21runrttasks10:22:423
10076992019,1cyclictest0-21swapper/209:34:152
1007499202,17cyclictest10-21rcuc/010:25:370
276292190,1sleep30-21swapper/308:40:183
10077991917,1cyclictest0-21swapper/311:07:113
10077991917,1cyclictest0-21swapper/310:15:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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