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2026-03-19 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Wed Mar 18, 2026 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2698821040,0sleep126989-21sshd11:08:321
246852900,0sleep00-21swapper/011:54:150
94892860,1sleep19491-21id10:09:361
215402670,1sleep38-21rcu_preempt09:19:143
159342670,1sleep013459-21diskmemload09:30:080
289072600,0sleep30-21swapper/311:20:133
192862600,0sleep30-21swapper/311:07:513
593325823,9sleep20-21swapper/207:09:132
233532580,1sleep228-21rcuc/210:45:142
135142580,0sleep230-21ksoftirqd/211:21:392
114072570,0sleep20-21swapper/211:30:092
65302560,0sleep339-21ksoftirqd/312:29:563
605125623,9sleep10-21swapper/107:09:481
168552560,1sleep016849-21cp09:55:480
115072560,1sleep00-21swapper/010:41:160
45542550,3sleep228-21rcuc/211:55:162
3292550,0sleep2291ktimersoftd/211:17:392
126442550,0sleep119-21rcuc/110:01:101
252132540,1sleep119-21rcuc/112:08:371
252132540,1sleep119-21rcuc/112:08:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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