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2026-08-06 - 03:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Aug 06, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3157021100,0sleep131552-21sshd22:26:281
2582521030,0sleep10-21swapper/123:18:471
628021010,0sleep10-21swapper/121:31:321
70812890,0sleep07042-21sshd23:55:170
98826127,30sleep00-21swapper/019:08:040
174732580,0sleep31866-21runrttasks21:35:263
3151025724,4sleep10-21swapper/119:05:121
43652560,0sleep20-21swapper/221:28:282
290042560,0sleep3381ktimersoftd/323:19:053
101025629,9sleep20-21swapper/219:08:222
90152530,0sleep38985-21sshd00:16:023
291552530,0sleep30-21swapper/322:52:423
225162530,0sleep20-21swapper/223:36:042
137062530,0sleep10-21swapper/123:08:541
102125340,9sleep30-21swapper/319:08:323
315302520,0sleep20-21swapper/222:38:152
258992520,1sleep00-21swapper/023:12:550
49182510,0sleep20-21swapper/200:18:422
85372490,0sleep11866-21runrttasks22:36:051
270162490,1sleep126997-21sshd00:00:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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