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2025-11-27 - 22:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Nov 27, 2025 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1564121240,0sleep015624-21sshd10:15:350
74822800,0sleep37472-21sshd10:19:063
2764926427,19sleep10-21swapper/107:07:061
4832570,1sleep020912-21diskmemload12:35:520
201142570,0sleep120912-21diskmemload09:46:521
48932550,0sleep20-21swapper/210:55:592
246482540,1sleep21819-21runrttasks10:54:152
30442530,1sleep32814199cyclictest12:08:473
2756125330,9sleep20-21swapper/207:05:592
81962520,0sleep30-21swapper/309:33:323
79022510,0sleep00-21swapper/010:01:530
286272510,0sleep30-21swapper/310:42:183
2766525132,15sleep30-21swapper/307:07:163
2752925128,19sleep00-21swapper/007:05:330
236202510,0sleep20-21swapper/210:16:362
259552500,1sleep12813999cyclictest09:10:251
58092490,0sleep20-21swapper/212:36:262
87812470,0sleep10-21swapper/109:41:311
30242450,0sleep03022-21sshd11:28:580
185162450,0sleep00-21swapper/011:38:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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