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2026-03-08 - 08:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sun Mar 08, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1586921110,0sleep015852-21sshd23:06:000
245792910,0sleep20-21swapper/222:20:592
171002900,0sleep10-21swapper/100:09:071
171002900,0sleep10-21swapper/100:09:071
249712630,0sleep20-21swapper/221:15:152
225662610,1sleep10-21swapper/121:23:411
216962610,1sleep321564-21wc19:10:003
307082600,1sleep330707-21sshd00:35:583
10892590,0sleep10-21swapper/121:35:591
72102580,1sleep07135-21sshd21:25:110
314782580,1sleep131477-21id22:01:341
207322580,1sleep30-21swapper/323:12:123
306632570,1sleep11734-21runrttasks21:15:441
197222570,1sleep319687-21sshd22:46:203
174302570,0sleep00-21swapper/022:17:320
324622550,1sleep337-21rcuc/323:36:033
24172550,0sleep30-21swapper/321:53:193
105372550,0sleep30-21swapper/321:28:193
233992540,0sleep323387-21sshd23:32:273
96462520,0sleep30-21swapper/321:22:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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