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2026-08-15 - 04:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Aug 15, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
119542900,0sleep339-21ksoftirqd/300:00:053
272992750,0sleep00-21swapper/023:18:270
173402730,0sleep00-21swapper/022:17:260
364326327,19sleep30-21swapper/319:05:123
14192620,7sleep121-21ksoftirqd/121:21:301
23142600,1sleep12298-21sshd23:47:401
213302600,0sleep20-21swapper/222:52:102
59012590,0sleep20-21swapper/200:28:162
183612590,1sleep28-21rcu_preempt23:57:442
23282570,0sleep30-21swapper/322:19:013
232562570,2sleep30-21swapper/322:58:033
179572570,0sleep10-21swapper/122:20:191
74462550,0sleep1201ktimersoftd/121:53:361
218202550,1sleep01707-21sshd21:40:250
194622550,0sleep00-21swapper/023:26:160
173432550,0sleep30-21swapper/322:11:403
173432550,0sleep30-21swapper/322:11:403
575125432,18sleep00-21swapper/019:09:420
110072540,0sleep131123-21diskmemload21:13:531
67432530,0sleep00-21swapper/021:47:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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