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2026-04-09 - 10:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Apr 09, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143342620,2sleep10-21swapper/122:29:191
1871826026,16sleep00-21swapper/019:08:590
111632600,1sleep31510-21nfsd22:26:053
83382580,1sleep30-21swapper/322:14:273
83382580,1sleep30-21swapper/322:14:273
269272570,1sleep226928-21sshd23:04:542
170712570,1sleep30-21swapper/322:09:303
73232560,2sleep119-21rcuc/123:52:001
177052560,0sleep10-21swapper/123:32:451
85942550,0sleep28583-21sshd21:25:262
272522550,0sleep041ktimersoftd/022:53:260
261842540,0sleep126181-21sshd23:10:261
225002540,0sleep30-21swapper/323:15:523
17322540,0sleep00-21swapper/000:37:430
298032530,1sleep026301-21diskmemload00:20:040
298032530,1sleep026301-21diskmemload00:20:040
145412530,1sleep114537-21sshd23:20:551
107532530,0sleep20-21swapper/223:06:142
246682520,0sleep10-21swapper/121:32:421
14572520,0sleep30-21swapper/321:33:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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