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2026-03-01 - 07:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Feb 28, 2026 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170182650,0sleep316999-21sshd11:09:163
287262630,1sleep328728-21id11:27:133
188462630,0sleep20-21swapper/209:47:132
265802620,1sleep31734-21runrttasks10:47:243
144282610,0sleep20-21swapper/211:45:442
131822600,2sleep2590099cyclictest09:32:352
318982580,0sleep031879-21sshd09:59:450
20532580,0sleep20-21swapper/211:36:102
182652570,0sleep30-21swapper/309:10:203
300262560,0sleep230024-21sshd10:19:232
236272560,0sleep00-21swapper/010:07:260
223052560,1sleep01734-21runrttasks12:11:540
247412550,0sleep10-21swapper/112:12:071
163792550,0sleep116329-21sshd11:31:491
240162540,0sleep10-21swapper/110:47:091
208462540,0sleep30-21swapper/309:33:163
125212540,1sleep027721-21minicom10:12:070
486825324,25sleep30-21swapper/307:06:093
280582530,0sleep228057-21sshd12:18:052
61212520,0sleep30-21swapper/309:17:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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