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2026-06-12 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Jun 12, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189302930,0sleep118931-21sshd10:23:091
28432890,0sleep32845-21id12:22:343
178262660,1sleep10-21swapper/109:54:081
316132630,1sleep331607-21ls09:55:183
281692580,0sleep00-21swapper/011:07:030
122882580,0sleep012284-21bash10:34:090
19122570,1sleep10-21swapper/109:24:031
19122570,1sleep10-21swapper/109:24:031
311292560,1sleep131107-21sshd12:33:411
185692560,0sleep00-21swapper/012:00:550
195372550,0sleep30-21swapper/309:25:303
101712550,0sleep20-21swapper/209:19:042
300732540,1sleep330070-21bash09:35:073
2857825422,4sleep30-21swapper/307:07:523
48632530,0sleep20-21swapper/212:19:572
40652530,0sleep10-21swapper/110:53:301
2819725325,9sleep00-21swapper/007:05:570
268922530,1sleep30-21swapper/311:01:093
208812530,1sleep320870-21sshd11:17:593
171052530,0sleep217085-21sshd09:42:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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