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2026-03-28 - 13:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Mar 28, 2026 00:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
280532980,2sleep02818299cyclictest00:14:150
39042940,0sleep10-21swapper/123:40:391
299962870,0sleep00-21swapper/023:54:280
13072840,0sleep00-21swapper/023:37:370
2521226124,9sleep20-21swapper/219:05:122
136282610,0sleep00-21swapper/022:16:080
3882590,0sleep10-21swapper/100:17:301
273822590,0sleep21734-21runrttasks20:00:182
12072590,1sleep11596-21sshd23:46:081
241282580,0sleep20-21swapper/223:13:592
2757325723,18sleep10-21swapper/119:08:151
225382570,0sleep00-21swapper/021:31:290
212562570,1sleep221255-21timerwakeupswit22:05:252
135532570,1sleep31734-21runrttasks23:07:193
11572570,1sleep10-21swapper/100:20:221
34612540,1sleep10-21swapper/122:52:121
25962540,1sleep32599-21sshd22:09:343
150782540,0sleep30-21swapper/323:53:073
325652530,0sleep30-21swapper/323:26:033
78412520,1sleep20-21swapper/223:55:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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