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2026-03-20 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Mar 20, 2026 00:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
161792940,0sleep30-21swapper/323:23:453
123912910,1sleep312394-21id00:32:253
144752860,0sleep30-21swapper/300:00:553
256572660,1sleep125639-21sshd23:36:011
166652620,0sleep016644-21sshd22:09:020
315472610,1sleep30-21swapper/300:05:203
315472610,1sleep30-21swapper/300:05:203
144152610,0sleep20-21swapper/223:43:432
144152610,0sleep20-21swapper/223:43:432
275082600,0sleep30-21swapper/322:58:533
84132590,1sleep030854-21diskmemload23:02:550
156442580,1sleep30-21swapper/321:31:283
226732570,1sleep022644-21sshd22:18:120
116812570,1sleep10-21swapper/121:16:471
69862550,0sleep36981-21sshd21:25:033
267882550,1sleep226791-21bash00:13:362
263072540,1sleep130854-21diskmemload21:23:521
226912540,0sleep00-21swapper/022:29:460
226192540,1sleep122618-21sshd21:37:511
226192540,1sleep122618-21sshd21:37:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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