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2026-03-14 - 16:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Mar 14, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
347621380,0sleep223089-21diskmemload11:03:452
1551627128,29sleep10-21swapper/107:09:111
51072620,1sleep119-21rcuc/112:30:371
44962600,1sleep01734-21runrttasks10:29:090
256742600,0sleep00-21swapper/010:07:540
256982590,1sleep20-21swapper/212:29:432
179602590,1sleep20-21swapper/211:42:432
316132580,1sleep10-21swapper/110:25:421
26522570,1sleep02639-21sshd12:27:360
6222560,1sleep30-21swapper/310:46:033
322462560,1sleep00-21swapper/012:10:050
56012550,1sleep25576-21sshd11:53:132
237262550,1sleep21734-21runrttasks10:10:332
183012550,0sleep20-21swapper/209:32:352
90592540,1sleep19056-21sshd12:19:371
243672520,0sleep123089-21diskmemload12:00:381
170942520,0sleep30-21swapper/309:35:203
5542510,0sleep10-21swapper/110:05:351
295402510,1sleep229524-21sshd11:32:092
280742510,0sleep20-21swapper/210:54:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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