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2026-04-21 - 18:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue Apr 21, 2026 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
775521030,0sleep37728-21sshd11:49:393
241242870,0sleep30-21swapper/311:23:593
213872660,0sleep00-21swapper/010:47:340
320372650,0sleep132034-21sshd11:27:411
312642630,1sleep031239-21sshd09:54:080
165422620,1sleep20-21swapper/211:59:312
6672600,0sleep337-21rcuc/309:54:213
334725924,19sleep10-21swapper/107:06:021
7962570,0sleep20-21swapper/209:30:072
298192570,1sleep229796-21sshd10:42:192
49902560,0sleep10-21swapper/111:07:061
115412560,1sleep011539-21bash09:58:210
310062550,1sleep230984-21sshd09:14:482
12232550,0sleep30-21swapper/310:27:343
326952540,0sleep00-21swapper/009:45:110
236472540,0sleep20-21swapper/211:20:492
77172530,0sleep30-21swapper/309:12:333
302262530,0sleep30-21swapper/309:20:383
23502530,0sleep30-21swapper/311:43:013
228822530,0sleep222871-21sshd10:56:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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