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2026-05-22 - 10:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri May 22, 2026 00:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
474121330,0sleep34737-21sshd21:35:183
140672980,0sleep214052-21sshd00:26:432
325512930,0sleep10-21swapper/122:24:111
253192930,0sleep20-21swapper/223:50:142
63512900,1sleep0388999cyclictest22:36:120
31652900,0sleep20-21swapper/221:35:132
108472900,0sleep230-21ksoftirqd/222:22:122
31092640,1sleep10-21swapper/122:18:381
108572640,1sleep110837-21sshd21:15:351
283526022,9sleep00-21swapper/019:06:020
263762590,0sleep10-21swapper/100:07:401
297702580,0sleep30-21swapper/323:30:203
239042580,0sleep30-21swapper/323:35:323
266982570,1sleep10-21swapper/122:32:161
64992560,0sleep2291ktimersoftd/223:36:562
226032560,0sleep00-21swapper/000:30:230
169172560,1sleep216912-21sshd21:10:252
324412550,1sleep332420-21sshd23:50:473
200172550,0sleep1201ktimersoftd/123:52:381
87022540,0sleep2291ktimersoftd/200:03:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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