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2026-05-07 - 21:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu May 07, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15262980,0sleep20-21swapper/212:00:262
67582650,1sleep16757-21sshd10:55:341
73542600,1sleep27352-21bash10:15:492
249742600,1sleep124973-21bash11:34:121
247612590,0sleep00-21swapper/011:02:540
264672570,0sleep30-21swapper/310:03:243
167552560,0sleep30-21swapper/310:59:253
216192550,1sleep221615-21sshd12:13:402
2295725427,8sleep00-21swapper/007:07:580
2295725427,8sleep00-21swapper/007:07:580
98592530,0sleep30-21swapper/309:39:163
222872530,0sleep322270-21sshd09:51:383
142392520,0sleep10-21swapper/111:07:401
4612510,1sleep30-21swapper/311:43:253
4612510,1sleep30-21swapper/311:43:243
2273825124,8sleep20-21swapper/207:06:522
2273825124,8sleep20-21swapper/207:06:512
186442510,0sleep20-21swapper/210:11:082
89252500,0sleep119-21rcuc/110:21:421
215912500,0sleep228-21rcuc/211:19:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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