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2026-04-07 - 14:54
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Tue Apr 07, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
150433199323,22cyclictest157-21kworker/2:1-events_freezable2
150433199316,19cyclictest157-21kworker/2:1-events_freezable2
150433199314,21cyclictest157-21kworker/2:1-events_freezable2
150433199313,21cyclictest157-21kworker/2:1-events_freezable2
150433199307,19cyclictest157-21kworker/2:1-events_freezable2
150433199294,20cyclictest157-21kworker/2:1-events_freezable2
150433199294,19cyclictest157-21kworker/2:1-events_freezable2
150433199294,19cyclictest157-21kworker/2:1-events_freezable2
150433199294,18cyclictest157-21kworker/2:1-events_freezable2
150433199294,18cyclictest157-21kworker/2:1-events_freezable2
150433199293,20cyclictest157-21kworker/2:1-events_freezable2
150433199285,19cyclictest157-21kworker/2:1-events_freezable2
150433199284,20cyclictest157-21kworker/2:1-events_freezable2
150433199284,17cyclictest157-21kworker/2:1-events_freezable2
150433199282,20cyclictest157-21kworker/2:1-events_freezable2
150433199282,19cyclictest157-21kworker/2:1-events_freezable2
150433199273,18cyclictest157-21kworker/2:1-events_freezable2
150433199273,18cyclictest157-21kworker/2:1-events_freezable2
150433199272,19cyclictest157-21kworker/2:1-events_freezable2
150433199272,19cyclictest157-21kworker/2:1-events_freezable2
150433199272,18cyclictest157-21kworker/2:1-events_freezable2
150433199264,15cyclictest157-21kworker/2:1-events_freezable2
150433199263,19cyclictest157-21kworker/2:1-events_freezable2
150433199262,18cyclictest157-21kworker/2:1-events_freezable2
150433199262,18cyclictest157-21kworker/2:1-events_freezable2
150433199262,18cyclictest157-21kworker/2:1-events_freezable2
150433199262,18cyclictest157-21kworker/2:1-events_freezable2
150433199262,18cyclictest157-21kworker/2:1-events_freezable2
150433199261,18cyclictest157-21kworker/2:1-events_freezable2
150433199255,16cyclictest157-21kworker/2:1-events_freezable2
150433199255,15cyclictest157-21kworker/2:1-events_freezable2
150433199254,15cyclictest157-21kworker/2:1-events_freezable2
150433199254,14cyclictest157-21kworker/2:1-events_freezable2
150433199254,14cyclictest157-21kworker/2:1-events_freezable2
150433199253,15cyclictest157-21kworker/2:1-events_freezable2
150433199252,17cyclictest157-21kworker/2:1-events_freezable2
150433199252,17cyclictest157-21kworker/2:1-events_freezable2
150433199251,18cyclictest157-21kworker/2:1-events_freezable2
150433199251,18cyclictest157-21kworker/2:1-events_freezable2
150433199251,18cyclictest157-21kworker/2:1-events_freezable2
150433199251,17cyclictest157-21kworker/2:1-events_freezable2
150433199251,17cyclictest157-21kworker/2:1-events_freezable2
150433199243,17cyclictest157-21kworker/2:1-events_freezable2
150433199243,15cyclictest157-21kworker/2:1-events_freezable2
150433199242,17cyclictest157-21kworker/2:1-events_freezable2
150433199242,17cyclictest157-21kworker/2:1-events_freezable2
150433199242,16cyclictest157-21kworker/2:1-events_freezable2
150433199241,17cyclictest157-21kworker/2:1-events_freezable2
150433199241,17cyclictest157-21kworker/2:1-events_freezable2
150433199241,17cyclictest157-21kworker/2:1-events_freezable2
150433199234,13cyclictest157-21kworker/2:1-events_freezable2
150433199233,14cyclictest157-21kworker/2:1-events_freezable2
150433199233,14cyclictest157-21kworker/2:1-events_freezable2
150433199232,16cyclictest157-21kworker/2:1-events_freezable2
150433199231,17cyclictest157-21kworker/2:1-events_freezable2
150433199230,16cyclictest157-21kworker/2:1-events_freezable2
150433199223,13cyclictest157-21kworker/2:1-events_freezable2
150433199222,15cyclictest157-21kworker/2:1-events_freezable2
150433199220,18cyclictest157-21kworker/2:1-events_freezable2
150433199214,15cyclictest157-21kworker/2:1-events_freezable2
150433199213,12cyclictest157-21kworker/2:1-events_freezable2
150433199212,14cyclictest157-21kworker/2:1-events_freezable2
150433199212,13cyclictest157-21kworker/2:1-events_freezable2
150433199204,11cyclictest157-21kworker/2:1-events_freezable2
150433199202,17cyclictest157-21kworker/2:1-events_freezable2
150433199201,15cyclictest157-21kworker/2:1-events_freezable2
15043319951,2cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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