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2026-01-27 - 19:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Tue Jan 27, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180254399122,5cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399103,3cyclictest0-21swapper/22
180254399102,4cyclictest0-21swapper/22
180254399102,4cyclictest0-21swapper/22
180254399102,3cyclictest0-21swapper/22
180254399101,5cyclictest0-21swapper/22
180254399101,5cyclictest0-21swapper/22
180254399101,5cyclictest0-21swapper/22
180254399101,5cyclictest0-21swapper/22
180254399101,4cyclictest0-21swapper/22
180254399101,4cyclictest0-21swapper/22
180254399101,4cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025439992,3cyclictest0-21swapper/22
18025399984,2cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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