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2026-04-11 - 18:50
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Sat Apr 11, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
241685099338,19cyclictest157-21kworker/2:1-events_freezable2
241685099337,19cyclictest157-21kworker/2:1-events_freezable2
241685099336,20cyclictest157-21kworker/2:1-events_freezable2
241685099327,18cyclictest157-21kworker/2:1-events_freezable2
241685099317,18cyclictest157-21kworker/2:1-events_freezable2
241685099316,18cyclictest157-21kworker/2:1-events_freezable2
241685099315,19cyclictest157-21kworker/2:1-events_freezable2
241685099315,19cyclictest157-21kworker/2:1-events_freezable2
241685099308,18cyclictest157-21kworker/2:1-events_freezable2
241685099308,17cyclictest157-21kworker/2:1-events_freezable2
241685099306,18cyclictest157-21kworker/2:1-events_freezable2
241685099306,18cyclictest157-21kworker/2:1-events_freezable2
241685099306,18cyclictest157-21kworker/2:1-events_freezable2
241685099306,17cyclictest157-21kworker/2:1-events_freezable2
241685099306,17cyclictest157-21kworker/2:1-events_freezable2
241685099305,18cyclictest157-21kworker/2:1-events_freezable2
241685099303,20cyclictest157-21kworker/2:1-events_freezable2
241685099297,18cyclictest157-21kworker/2:1-events_freezable2
241685099296,17cyclictest157-21kworker/2:1-events_freezable2
241685099296,17cyclictest157-21kworker/2:1-events_freezable2
241685099296,17cyclictest157-21kworker/2:1-events_freezable2
241685099296,17cyclictest157-21kworker/2:1-events_freezable2
241685099295,18cyclictest157-21kworker/2:1-events_freezable2
241685099295,18cyclictest157-21kworker/2:1-events_freezable2
241685099295,17cyclictest157-21kworker/2:1-events_freezable2
241685099286,18cyclictest157-21kworker/2:1-events_freezable2
241685099286,17cyclictest157-21kworker/2:1-events_freezable2
241685099286,17cyclictest157-21kworker/2:1-events_freezable2
241685099286,16cyclictest157-21kworker/2:1-events_freezable2
241685099285,18cyclictest157-21kworker/2:1-events_freezable2
241685099285,17cyclictest157-21kworker/2:1-events_freezable2
241685099284,18cyclictest157-21kworker/2:1-events_freezable2
241685099284,18cyclictest157-21kworker/2:1-events_freezable2
241685099284,18cyclictest157-21kworker/2:1-events_freezable2
241685099284,17cyclictest157-21kworker/2:1-events_freezable2
241685099284,17cyclictest157-21kworker/2:1-events_freezable2
241685099283,18cyclictest157-21kworker/2:1-events_freezable2
241685099283,18cyclictest157-21kworker/2:1-events_freezable2
241685099276,16cyclictest157-21kworker/2:1-events_freezable2
241685099275,18cyclictest157-21kworker/2:1-events_freezable2
241685099274,18cyclictest157-21kworker/2:1-events_freezable2
241685099274,16cyclictest157-21kworker/2:1-events_freezable2
241685099266,16cyclictest157-21kworker/2:1-events_freezable2
241685099266,15cyclictest157-21kworker/2:1-events_freezable2
241685099265,16cyclictest157-21kworker/2:1-events_freezable2
241685099265,15cyclictest157-21kworker/2:1-events_freezable2
241685099264,16cyclictest157-21kworker/2:1-events_freezable2
241685099264,16cyclictest157-21kworker/2:1-events_freezable2
241685099263,17cyclictest157-21kworker/2:1-events_freezable2
241685099263,16cyclictest157-21kworker/2:1-events_freezable2
241685099262,17cyclictest157-21kworker/2:1-events_freezable2
241685099255,15cyclictest157-21kworker/2:1-events_freezable2
241685099255,15cyclictest157-21kworker/2:1-events_freezable2
241685099255,15cyclictest157-21kworker/2:1-events_freezable2
241685099254,16cyclictest157-21kworker/2:1-events_freezable2
241685099252,16cyclictest157-21kworker/2:1-events_freezable2
241685099252,16cyclictest157-21kworker/2:1-events_freezable2
241685099252,16cyclictest157-21kworker/2:1-events_freezable2
241685099245,14cyclictest157-21kworker/2:1-events_freezable2
241685099243,17cyclictest157-21kworker/2:1-events_freezable2
241685099243,16cyclictest157-21kworker/2:1-events_freezable2
241685099243,15cyclictest157-21kworker/2:1-events_freezable2
241685099243,14cyclictest157-21kworker/2:1-events_freezable2
241685099234,14cyclictest157-21kworker/2:1-events_freezable2
241685099234,14cyclictest157-21kworker/2:1-events_freezable2
241685099233,15cyclictest157-21kworker/2:1-events_freezable2
24168509961,2cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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