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2026-02-17 - 20:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Tue Feb 17, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
251191799272,21cyclictest157-21kworker/2:1-events_freezable2
251191799234,14cyclictest157-21kworker/2:1-events_freezable2
251191799221,14cyclictest157-21kworker/2:1-events_freezable2
251191799211,13cyclictest157-21kworker/2:1-events_freezable2
251191799202,15cyclictest157-21kworker/2:1-events_freezable2
251191799201,14cyclictest157-21kworker/2:1-events_freezable2
251191799201,12cyclictest157-21kworker/2:1-events_freezable2
251191799201,12cyclictest157-21kworker/2:1-events_freezable2
251191799201,12cyclictest157-21kworker/2:1-events_freezable2
251191799191,13cyclictest157-21kworker/2:1-events_freezable2
251191799191,13cyclictest157-21kworker/2:1-events_freezable2
251191799191,13cyclictest157-21kworker/2:1-events_freezable2
251191799191,12cyclictest157-21kworker/2:1-events_freezable2
251191799191,12cyclictest157-21kworker/2:1-events_freezable2
251191799191,12cyclictest157-21kworker/2:1-events_freezable2
251191799191,11cyclictest157-21kworker/2:1-events_freezable2
251191799190,13cyclictest157-21kworker/2:1-events_freezable2
251191799190,13cyclictest157-21kworker/2:1-events_freezable2
251191799190,12cyclictest157-21kworker/2:1-events_freezable2
251191799182,10cyclictest157-21kworker/2:1-events_freezable2
251191799181,11cyclictest157-21kworker/2:1-events_freezable2
251191799181,11cyclictest157-21kworker/2:1-events_freezable2
251191799181,11cyclictest157-21kworker/2:1-events_freezable2
251191799181,10cyclictest157-21kworker/2:1-events_freezable2
251191799181,10cyclictest157-21kworker/2:1-events_freezable2
251191799181,10cyclictest157-21kworker/2:1-events_freezable2
251191799181,10cyclictest157-21kworker/2:1-events_freezable2
251191799181,10cyclictest157-21kworker/2:1-events_freezable2
251191999171,2cyclictest0-21swapper/22
251191999171,2cyclictest0-21swapper/22
251191799172,9cyclictest157-21kworker/2:1-events_freezable2
251191799171,9cyclictest157-21kworker/2:1-events_freezable2
251191799171,9cyclictest157-21kworker/2:1-events_freezable2
251191799171,9cyclictest157-21kworker/2:1-events_freezable2
251191799171,9cyclictest157-21kworker/2:1-events_freezable2
251191799171,11cyclictest157-21kworker/2:1-events_freezable2
251191799171,11cyclictest157-21kworker/2:1-events_freezable2
251191999160,3cyclictest0-21swapper/22
251191799161,9cyclictest157-21kworker/2:1-events_freezable2
251191799161,9cyclictest157-21kworker/2:1-events_freezable2
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,9cyclictest0-21swapper/22
251191799161,10cyclictest157-21kworker/2:1-events_freezable2
251191799161,10cyclictest157-21kworker/2:1-events_freezable2
251191799160,9cyclictest157-21kworker/2:1-events_freezable2
251191999151,2cyclictest0-21swapper/22
251191999151,2cyclictest0-21swapper/22
251191799151,9cyclictest0-21swapper/22
251191799151,9cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191799151,8cyclictest0-21swapper/22
251191999141,2cyclictest0-21swapper/22
251191999141,2cyclictest0-21swapper/22
251191999121,2cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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