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2026-04-11 - 02:39
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Fri Apr 10, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
323100799347,19cyclictest157-21kworker/2:1-events_freezable2
323100799326,18cyclictest157-21kworker/2:1-events_freezable2
323100799324,19cyclictest157-21kworker/2:1-events_freezable2
323100799317,17cyclictest157-21kworker/2:1-events_freezable2
323100799314,19cyclictest157-21kworker/2:1-events_freezable2
323100799314,18cyclictest157-21kworker/2:1-events_freezable2
323100799314,18cyclictest157-21kworker/2:1-events_freezable2
323100799304,19cyclictest157-21kworker/2:1-events_freezable2
323100799294,17cyclictest157-21kworker/2:1-events_freezable2
323100799294,17cyclictest157-21kworker/2:1-events_freezable2
323100799293,17cyclictest157-21kworker/2:1-events_freezable2
323100799292,17cyclictest157-21kworker/2:1-events_freezable2
323100799292,17cyclictest157-21kworker/2:1-events_freezable2
323100799285,16cyclictest157-21kworker/2:1-events_freezable2
323100799284,16cyclictest157-21kworker/2:1-events_freezable2
323100799284,15cyclictest157-21kworker/2:1-events_freezable2
323100799283,17cyclictest157-21kworker/2:1-events_freezable2
323100799283,16cyclictest157-21kworker/2:1-events_freezable2
323100799282,16cyclictest157-21kworker/2:1-events_freezable2
323100799282,16cyclictest157-21kworker/2:1-events_freezable2
323100799282,16cyclictest157-21kworker/2:1-events_freezable2
323100799281,18cyclictest157-21kworker/2:1-events_freezable2
323100799275,14cyclictest157-21kworker/2:1-events_freezable2
323100799274,14cyclictest157-21kworker/2:1-events_freezable2
323100799274,13cyclictest157-21kworker/2:1-events_freezable2
323100799272,16cyclictest157-21kworker/2:1-events_freezable2
323100799272,16cyclictest157-21kworker/2:1-events_freezable2
323100799272,16cyclictest157-21kworker/2:1-events_freezable2
323100799271,17cyclictest157-21kworker/2:1-events_freezable2
323100799271,17cyclictest157-21kworker/2:1-events_freezable2
323100799271,16cyclictest157-21kworker/2:1-events_freezable2
323100799262,16cyclictest157-21kworker/2:1-events_freezable2
323100799262,16cyclictest157-21kworker/2:1-events_freezable2
323100799262,16cyclictest157-21kworker/2:1-events_freezable2
323100799261,16cyclictest157-21kworker/2:1-events_freezable2
323100799260,17cyclictest157-21kworker/2:1-events_freezable2
323100799255,13cyclictest157-21kworker/2:1-events_freezable2
323100799255,13cyclictest157-21kworker/2:1-events_freezable2
323100799254,12cyclictest157-21kworker/2:1-events_freezable2
323100799245,13cyclictest157-21kworker/2:1-events_freezable2
323100799235,12cyclictest157-21kworker/2:1-events_freezable2
323100799234,13cyclictest157-21kworker/2:1-events_freezable2
323100799230,16cyclictest157-21kworker/2:1-events_freezable2
323100799225,12cyclictest157-21kworker/2:1-events_freezable2
323100799225,11cyclictest157-21kworker/2:1-events_freezable2
323100799223,13cyclictest157-21kworker/2:1-events_freezable2
323100799223,13cyclictest157-21kworker/2:1-events_freezable2
323100799223,13cyclictest157-21kworker/2:1-events_freezable2
323100799221,16cyclictest157-21kworker/2:1-events_freezable2
323100799221,16cyclictest157-21kworker/2:1-events_freezable2
323100799221,15cyclictest157-21kworker/2:1-events_freezable2
323100799220,16cyclictest157-21kworker/2:1-events_freezable2
323100799215,13cyclictest157-21kworker/2:1-events_freezable2
323100799215,11cyclictest157-21kworker/2:1-events_freezable2
323100799214,13cyclictest157-21kworker/2:1-events_freezable2
323100799214,12cyclictest157-21kworker/2:1-events_freezable2
323100799213,13cyclictest157-21kworker/2:1-events_freezable2
323100799212,15cyclictest157-21kworker/2:1-events_freezable2
323100799211,15cyclictest157-21kworker/2:1-events_freezable2
323100799204,12cyclictest157-21kworker/2:1-events_freezable2
323100799203,12cyclictest157-21kworker/2:1-events_freezable2
323100799201,15cyclictest157-21kworker/2:1-events_freezable2
323100799193,12cyclictest157-21kworker/2:1-events_freezable2
323100799193,11cyclictest157-21kworker/2:1-events_freezable2
323100799192,16cyclictest157-21kworker/2:1-events_freezable2
323100799162,12cyclictest157-21kworker/2:1-events_freezable2
32309979984,3cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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