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2026-06-15 - 20:19
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackaslot4.osadl.org (updated Mon Jun 15, 2026 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
14607199348,20cyclictest157-21kworker/2:1-events_freezable2
14607199336,20cyclictest157-21kworker/2:1-events_freezable2
14607199327,19cyclictest157-21kworker/2:1-events_freezable2
14607199327,19cyclictest157-21kworker/2:1-events_freezable2
14607199317,18cyclictest157-21kworker/2:1-events_freezable2
14607199316,19cyclictest157-21kworker/2:1-events_freezable2
14607199308,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,19cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199306,18cyclictest157-21kworker/2:1-events_freezable2
14607199297,18cyclictest157-21kworker/2:1-events_freezable2
14607199296,18cyclictest157-21kworker/2:1-events_freezable2
14607199296,18cyclictest157-21kworker/2:1-events_freezable2
14607199296,18cyclictest157-21kworker/2:1-events_freezable2
14607199296,17cyclictest157-21kworker/2:1-events_freezable2
14607199296,17cyclictest157-21kworker/2:1-events_freezable2
14607199296,17cyclictest157-21kworker/2:1-events_freezable2
14607199296,17cyclictest157-21kworker/2:1-events_freezable2
14607199295,18cyclictest157-21kworker/2:1-events_freezable2
14607199295,18cyclictest157-21kworker/2:1-events_freezable2
14607199287,15cyclictest157-21kworker/2:1-events_freezable2
14607199285,18cyclictest157-21kworker/2:1-events_freezable2
14607199285,17cyclictest157-21kworker/2:1-events_freezable2
14607199284,19cyclictest157-21kworker/2:1-events_freezable2
14607199284,18cyclictest157-21kworker/2:1-events_freezable2
14607199284,18cyclictest157-21kworker/2:1-events_freezable2
14607199283,18cyclictest157-21kworker/2:1-events_freezable2
14607199276,17cyclictest157-21kworker/2:1-events_freezable2
14607199276,16cyclictest157-21kworker/2:1-events_freezable2
14607199276,16cyclictest157-21kworker/2:1-events_freezable2
14607199275,18cyclictest157-21kworker/2:1-events_freezable2
14607199275,17cyclictest157-21kworker/2:1-events_freezable2
14607199275,17cyclictest157-21kworker/2:1-events_freezable2
14607199275,17cyclictest157-21kworker/2:1-events_freezable2
14607199275,16cyclictest157-21kworker/2:1-events_freezable2
14607199275,16cyclictest157-21kworker/2:1-events_freezable2
14607199275,16cyclictest157-21kworker/2:1-events_freezable2
14607199275,16cyclictest157-21kworker/2:1-events_freezable2
14607199275,16cyclictest157-21kworker/2:1-events_freezable2
14607199274,18cyclictest157-21kworker/2:1-events_freezable2
14607199274,18cyclictest157-21kworker/2:1-events_freezable2
14607199273,17cyclictest157-21kworker/2:1-events_freezable2
14607199266,16cyclictest157-21kworker/2:1-events_freezable2
14607199265,16cyclictest157-21kworker/2:1-events_freezable2
14607199265,16cyclictest157-21kworker/2:1-events_freezable2
14607199264,16cyclictest157-21kworker/2:1-events_freezable2
14607199264,16cyclictest157-21kworker/2:1-events_freezable2
14607199264,16cyclictest157-21kworker/2:1-events_freezable2
14607199263,17cyclictest157-21kworker/2:1-events_freezable2
14607199263,16cyclictest157-21kworker/2:1-events_freezable2
14607199255,16cyclictest157-21kworker/2:1-events_freezable2
14607199254,16cyclictest157-21kworker/2:1-events_freezable2
14607199254,16cyclictest157-21kworker/2:1-events_freezable2
14607199254,15cyclictest157-21kworker/2:1-events_freezable2
14607199254,15cyclictest157-21kworker/2:1-events_freezable2
14607199254,15cyclictest157-21kworker/2:1-events_freezable2
14607199253,17cyclictest157-21kworker/2:1-events_freezable2
14607199253,16cyclictest157-21kworker/2:1-events_freezable2
14607199244,16cyclictest157-21kworker/2:1-events_freezable2
14607199244,15cyclictest157-21kworker/2:1-events_freezable2
14607199244,15cyclictest157-21kworker/2:1-events_freezable2
14607199244,14cyclictest157-21kworker/2:1-events_freezable2
1460719981,5cyclictest0-21swapper/22
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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