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2025-08-30 - 00:47

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #a, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot4s.osadl.org (updated Fri Aug 29, 2025 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3647561997769,6cyclictest3739348-21kworker/u16:4+flush-179:03
3647561997163,6cyclictest3718395-21kworker/u16:2+events_unbound3
3647561996962,5cyclictest3722235-21kworker/u16:4+events_unbound3
3647561996658,6cyclictest3718395-21kworker/u16:2+events_unbound3
3647561996658,6cyclictest3707373-21kworker/u16:0+flush-179:03
3647547996657,7cyclictest3799039-21kworker/u16:5+flush-179:00
3647547996556,7cyclictest3768427-21kworker/u16:0+flush-179:00
3647561996457,5cyclictest3718395-21kworker/u16:2+flush-179:323
3647561996456,6cyclictest3805836-21kworker/u16:0+flush-179:03
3647551996455,7cyclictest3773104-21kworker/u16:3+flush-179:01
3647547996355,6cyclictest3671335-21kworker/u16:3+events_unbound0
3647561996153,6cyclictest3746900-21kworker/u16:1+events_unbound3
3647561996153,6cyclictest3739348-21kworker/u16:4+flush-179:03
3647561996050,8cyclictest3770573-21latency_hist3
3647561996050,8cyclictest3739348-21kworker/u16:4+events_unbound3
3647561996050,8cyclictest3739348-21kworker/u16:4+events_unbound3
3647556996051,7cyclictest3669574-21kworker/u16:4+flush-179:322
3647547995949,7cyclictest3669574-21kworker/u16:4+events_unbound0
3647561995851,5cyclictest3718395-21kworker/u16:2+events_unbound3
3647551995721,22cyclictest3824887-21sh1
3647561995648,6cyclictest3712053-21kworker/u16:1+events_unbound3
3647547995648,6cyclictest3671335-21kworker/u16:3+events_unbound0
3647561995546,7cyclictest3718395-21kworker/u16:2+events_unbound3
3647547995548,5cyclictest3838684-21kworker/u16:0+flush-179:320
3647547995546,7cyclictest3768427-21kworker/u16:0+flush-179:00
3647561995447,5cyclictest3828770-21kworker/u16:3+events_unbound3
3647561995446,6cyclictest3773104-21kworker/u16:3+events_unbound3
3647551995426,17cyclictest0-21swapper/11
3647551995341,9cyclictest519-21systemd-journal1
3647551995320,17cyclictest3814378-21rm1
3647547995344,7cyclictest3718395-21kworker/u16:2+events_unbound0
3647561995244,6cyclictest3799039-21kworker/u16:5+flush-179:03
3647561995244,6cyclictest3718395-21kworker/u16:2+flush-179:03
3647561995244,6cyclictest3718395-21kworker/u16:2+events_unbound3
3647561995244,6cyclictest3718395-21kworker/u16:2+events_unbound3
3647551995217,22cyclictest3732241-21date1
3647547995245,5cyclictest3671335-21kworker/u16:3+events_unbound0
3647561995143,6cyclictest3671335-21kworker/u16:3+flush-179:323
3647561995044,4cyclictest3823523-21kworker/u16:1+flush-179:03
3647561995043,5cyclictest3726995-21kworker/u16:1+events_unbound3
3647561995040,7cyclictest3799039-21kworker/u16:5+flush-179:03
3647551995020,16cyclictest3710075-21rm1
3647561994942,5cyclictest3746900-21kworker/u16:1+events_unbound3
3647556994938,8cyclictest3822552-21cat2
3647561994841,5cyclictest3746900-21kworker/u16:1+events_unbound3
3647561994841,5cyclictest3662274-21kworker/u16:1+flush-179:03
3647561994839,7cyclictest3823523-21kworker/u16:1+events_unbound3
3647561994839,7cyclictest3649167-21kworker/u16:0+events_unbound3
3647556994838,7cyclictest3848428-21kworker/u16:4+flush-179:02
3647551994817,14cyclictest3797974-21rm1
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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