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2025-12-15 - 00:55
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Note that this system runs a non-optimized debug kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 100 highest latencies:
System rackbslot0.osadl.org (updated Sun Dec 14, 2025 12:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5186
"cycles":100000000,5185
"load":"idle",5184
"condition":{5183
"clock":"2500"5181
"family":"x86",5180
"vendor":"Intel",5179
"processor":{5177
"dataset":"2024-01-08T15:38:16+0100"5175
"origin":"2024-01-08T12:43:22+0100",5174
"timestamps":{5173
"granularity":"microseconds"5171
6110:51:555169
41,10:51:355168
57,10:51:515167
43,10:51:375166
"maxima":[5165
010:50:545162
0,10:50:545161
0,10:50:545160
0,10:50:545159
0,10:50:545158
0,10:50:545157
0,10:50:545156
0,10:50:545155
0,10:50:545154
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0,10:50:545147
0,10:50:545146
0,10:50:545145
0,10:50:545144
0,10:50:545143
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0,10:50:545139
0,10:50:545138
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0,10:50:545135
0,10:50:545134
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0,10:50:545132
0,10:50:545131
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0,10:50:545121
0,10:50:545120
0,10:50:545119
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0,10:50:545104
0,10:50:545103
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0,10:50:545099
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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