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2026-02-21 - 23:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 21, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2301826011,17sleep00-21swapper/006:30:000
23430995816,37cyclictest21-21ksoftirqd/110:01:541
2344799575,46cyclictest0-21swapper/310:57:333
2285025712,16sleep30-21swapper/306:27:583
2344799564,46cyclictest0-21swapper/310:40:333
2343999564,46cyclictest0-21swapper/210:15:232
2343099564,46cyclictest0-21swapper/109:21:551
2343099564,45cyclictest0-21swapper/111:28:321
186492560,3sleep1201ktimersoftd/109:36:561
2343999555,8cyclictest0-21swapper/210:03:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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