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2026-02-06 - 12:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Feb 06, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207532640,6sleep10-21swapper/123:20:551
16553996252,5cyclictest21-21ksoftirqd/119:40:181
1655399604,50cyclictest0-21swapper/121:31:061
1655399603,9cyclictest0-21swapper/120:37:251
1655399603,51cyclictest0-21swapper/119:32:211
1654899597,46cyclictest0-21swapper/022:37:330
1626825911,17sleep00-21swapper/018:39:430
1655999585,47cyclictest0-21swapper/223:51:512
1655399574,48cyclictest0-21swapper/123:55:371
1655399573,8cyclictest0-21swapper/121:47:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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