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2026-01-24 - 20:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sat Jan 24, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59062960,3sleep3361ktimersoftd/310:52:043
2715799752,67cyclictest30029-21ssh11:22:333
2715799732,65cyclictest416-21/usr/sbin/munin08:27:213
2715799702,62cyclictest29124-21/usr/sbin/munin08:17:263
2715799702,62cyclictest10884-21ssh09:32:223
2715799693,59cyclictest23546-21/usr/sbin/munin11:57:263
2715799685,56cyclictest0-21swapper/311:12:273
2715799683,58cyclictest9175-21ssh09:30:493
2715799682,60cyclictest17418-21ssh10:23:263
2715799682,59cyclictest19196-21interrupts11:52:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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