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2026-01-19 - 03:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Mon Jan 19, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1051799603,52cyclictest0-21swapper/222:30:132
1051799584,49cyclictest0-21swapper/200:10:242
1051799584,48cyclictest0-21swapper/221:14:552
1051799565,45cyclictest0-21swapper/223:40:552
1051799564,7cyclictest0-21swapper/223:03:522
1051799564,46cyclictest0-21swapper/222:20:432
10517995546,5cyclictest29-21ksoftirqd/222:49:532
1051799554,44cyclictest0-21swapper/222:42:232
1051799554,44cyclictest0-21swapper/222:42:232
1051799553,46cyclictest0-21swapper/222:18:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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