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2026-02-25 - 23:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Wed Feb 25, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
403996051,5cyclictest21-21ksoftirqd/109:39:461
41499584,49cyclictest0-21swapper/308:06:393
40999584,48cyclictest0-21swapper/210:39:242
40999584,48cyclictest0-21swapper/209:30:222
323212579,17sleep00-21swapper/006:26:130
41499562,48cyclictest17073-21unixbench_multi10:00:153
40999565,44cyclictest0-21swapper/209:45:362
409995647,5cyclictest29-21ksoftirqd/210:49:452
40999563,6cyclictest0-21swapper/211:34:412
40999561,49cyclictest30363-21kworker/2:209:28:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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