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2026-02-20 - 15:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Feb 20, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
68982670,5sleep16895-21ksmtuned10:01:531
68982670,5sleep16895-21ksmtuned10:01:531
2609099594,50cyclictest0-21swapper/208:48:122
2609099594,49cyclictest0-21swapper/211:43:042
2609599585,47cyclictest0-21swapper/308:43:483
2609099576,8cyclictest0-21swapper/208:53:222
2609099573,48cyclictest0-21swapper/211:40:442
2609099573,48cyclictest0-21swapper/211:40:442
2609599564,47cyclictest0-21swapper/311:00:253
2609599563,47cyclictest26465-21grep11:12:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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