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2026-03-09 - 04:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Mon Mar 09, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
86102860,7sleep20-21swapper/221:58:222
2195099574,46cyclictest0-21swapper/220:58:462
2136225711,17sleep20-21swapper/218:19:342
2195699564,46cyclictest0-21swapper/321:56:353
2195099563,48cyclictest0-21swapper/223:03:352
2195099554,45cyclictest0-21swapper/223:33:332
2195099554,45cyclictest0-21swapper/221:22:102
21950995514,36cyclictest29-21ksoftirqd/222:23:342
21950995514,36cyclictest29-21ksoftirqd/222:23:342
21956995445,5cyclictest37-21ksoftirqd/323:18:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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