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2026-02-02 - 09:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 02, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1042999722,64cyclictest11028-21/usr/sbin/munin18:42:422
1009526015,39sleep20-21swapper/218:41:272
1043499594,50cyclictest0-21swapper/322:27:423
1042299594,19cyclictest0-21swapper/122:56:511
1043499575,46cyclictest0-21swapper/321:34:233
10429995725,27cyclictest32527-21sed20:52:542
1043499554,7cyclictest0-21swapper/320:44:243
1043499554,45cyclictest0-21swapper/321:20:543
1043499553,46cyclictest0-21swapper/322:09:333
1042299553,46cyclictest0-21swapper/122:21:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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