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2026-02-22 - 23:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sun Feb 22, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110102720,4sleep2281ktimersoftd/209:28:522
2007599597,46cyclictest0-21swapper/108:52:541
2007599597,46cyclictest0-21swapper/108:52:541
2007599595,48cyclictest0-21swapper/110:49:111
2007199595,48cyclictest638-21runrttasks07:16:540
20089995811,21cyclictest0-21swapper/310:23:513
20071995812,40cyclictest18888-21ssh08:56:040
20071995812,40cyclictest18888-21ssh08:56:040
2007199579,42cyclictest24428-21/usr/sbin/munin06:41:520
2007199565,44cyclictest0-21swapper/009:20:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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