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2026-02-21 - 11:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 21, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
750899814,46cyclictest0-21swapper/218:37:482
750899774,5cyclictest0-21swapper/221:07:392
750899765,46cyclictest0-21swapper/223:49:002
750899744,43cyclictest0-21swapper/222:59:382
750899734,42cyclictest0-21swapper/223:16:302
750899713,43cyclictest0-21swapper/222:23:162
7497997016,48cyclictest14786-21sed23:22:280
7497996913,50cyclictest9131-21ssh22:30:000
106672690,5sleep310654-21fschecks_count22:32:263
106672690,5sleep310654-21fschecks_count22:32:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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