You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-27 - 15:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Feb 27, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1259599728,5cyclictest0-21swapper/211:17:042
1259599722,64cyclictest1192-21ssh11:29:192
12595997210,5cyclictest0-21swapper/209:15:532
1259599715,60cyclictest0-21swapper/210:54:432
1259599715,60cyclictest0-21swapper/209:51:132
1259599715,59cyclictest0-21swapper/209:20:592
1259599714,7cyclictest0-21swapper/211:19:482
1259599714,7cyclictest0-21swapper/211:19:482
1259599713,9cyclictest0-21swapper/211:54:582
1259599706,58cyclictest0-21swapper/210:01:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional