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2026-02-28 - 13:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 28, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292542940,9sleep1201ktimersoftd/122:17:501
3097299765,64cyclictest0-21swapper/122:12:361
3097299764,6cyclictest0-21swapper/120:42:071
3097299764,29cyclictest0-21swapper/121:04:571
30972997610,5cyclictest0-21swapper/122:01:431
3097299748,60cyclictest0-21swapper/122:54:551
3097299739,58cyclictest0-21swapper/122:37:391
3097299737,5cyclictest0-21swapper/121:27:351
3097299735,61cyclictest0-21swapper/123:54:531
3097299735,61cyclictest0-21swapper/122:50:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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