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2026-02-16 - 14:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 16, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1842299782,70cyclictest2102-21ssh21:21:141
1842299782,69cyclictest26786-21ssh23:20:541
1842299775,66cyclictest0-21swapper/123:59:391
1842299752,66cyclictest18529-21/usr/sbin/munin20:00:191
1842299743,65cyclictest19428-21ssh23:11:101
1842299732,64cyclictest12899-21/usr/sbin/munin19:45:191
1842299713,62cyclictest24147-21/usr/sbin/munin20:15:191
1842299712,63cyclictest9153-21/usr/sbin/munin19:35:211
1842299712,63cyclictest29216-21ssh21:58:371
1842299712,31cyclictest1639-21/usr/sbin/munin19:15:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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