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2026-01-23 - 06:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa >
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 23, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
750799604,50cyclictest0-21swapper/223:32:502
750799574,46cyclictest0-21swapper/221:05:262
750799564,46cyclictest0-21swapper/221:47:262
750799564,45cyclictest0-21swapper/221:51:352
7500995616,34cyclictest26665-21sendmail_mailst21:38:131
750799557,42cyclictest0-21swapper/222:56:542
750099558,40cyclictest0-21swapper/121:32:071
750099554,45cyclictest0-21swapper/100:09:191
751199544,45cyclictest0-21swapper/323:28:473
750799543,46cyclictest5223-21ssh22:37:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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