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2026-01-22 - 04:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Thu Jan 22, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10618997212,54cyclictest6942-21sshd21:51:462
1061899715,59cyclictest0-21swapper/221:36:362
1061899715,59cyclictest0-21swapper/221:36:362
1061899715,59cyclictest0-21swapper/200:00:582
1061899705,7cyclictest0-21swapper/222:38:532
1061899705,58cyclictest0-21swapper/222:44:462
1061899705,58cyclictest0-21swapper/221:43:092
1061899705,58cyclictest0-21swapper/221:12:032
1061899695,57cyclictest0-21swapper/223:32:482
1061899695,57cyclictest0-21swapper/222:57:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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