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2026-02-05 - 11:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Thu Feb 05, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201742710,3sleep1201ktimersoftd/122:43:271
10734997113,33cyclictest4507-21aten_rbpower_en21:40:590
274942700,4sleep1201ktimersoftd/122:52:491
10750996210,45cyclictest0-21swapper/321:38:373
10739995950,5cyclictest21-21ksoftirqd/121:40:471
104092598,17sleep20-21swapper/218:39:492
1075099575,46cyclictest0-21swapper/321:51:463
10739995646,5cyclictest21-21ksoftirqd/121:50:471
1073999564,7cyclictest0-21swapper/100:02:431
1073999564,46cyclictest0-21swapper/120:40:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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