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2026-03-05 - 15:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Thu Mar 05, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1592999752,67cyclictest13430-21ssh08:46:381
1592999742,66cyclictest28830-21diskmemload09:14:031
1592999702,63cyclictest23423-21/usr/sbin/munin08:10:531
1592999702,62cyclictest29614-21/usr/sbin/munin07:00:551
15929997012,52cyclictest0-21swapper/108:31:181
15929997010,54cyclictest0-21swapper/108:50:381
1592999692,61cyclictest22139-21/usr/sbin/munin06:40:441
1592999692,61cyclictest17816-21/usr/sbin/munin07:55:451
1592999692,28cyclictest21420-21ssh08:57:491
15929996912,24cyclictest0-21swapper/110:12:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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