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2026-01-27 - 20:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 27, 2026 12:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1479499754,39cyclictest0-21swapper/310:43:093
1479499744,43cyclictest0-21swapper/311:42:383
1479499743,40cyclictest0-21swapper/309:34:203
1479499738,32cyclictest0-21swapper/309:05:153
1479499728,32cyclictest0-21swapper/309:51:143
1479499724,6cyclictest0-21swapper/310:12:503
1479499723,39cyclictest0-21swapper/311:06:283
1479499723,39cyclictest0-21swapper/311:06:283
14794997212,5cyclictest0-21swapper/311:31:463
14794997111,32cyclictest9017-21sshd11:12:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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