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2026-02-19 - 15:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Thu Feb 19, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24529997619,51cyclictest15393-21ssh09:29:101
24529997128,37cyclictest25914-21ls09:43:291
24529997128,37cyclictest25914-21ls09:43:291
24529996916,47cyclictest22257-21ssh11:06:171
24529996821,41cyclictest9236-21/usr/sbin/munin10:48:221
24529996819,14cyclictest15252-21/usr/sbin/munin07:33:271
24529996819,14cyclictest15252-21/usr/sbin/munin07:33:271
24529996621,39cyclictest5014-21ssh09:58:541
24529996616,43cyclictest0-21swapper/110:05:301
24529996615,44cyclictest0-21swapper/110:23:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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