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2026-01-30 - 19:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 30, 2026 12:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1240925912,17sleep20-21swapper/206:43:212
1268899583,29cyclictest563-21sshd08:53:270
1269299574,47cyclictest0-21swapper/108:45:551
1270699565,44cyclictest0-21swapper/312:05:303
1270699553,46cyclictest0-21swapper/311:37:113
1269299554,44cyclictest0-21swapper/110:15:531
1270699543,45cyclictest0-21swapper/307:09:063
1270699543,45cyclictest0-21swapper/307:09:063
1268899542,46cyclictest8171-21munin-run09:03:450
1270699534,7cyclictest0-21swapper/310:19:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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