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2026-02-27 - 00:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Thu Feb 26, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
390099753,66cyclictest13351-21/usr/sbin/munin08:19:403
390099753,66cyclictest13351-21/usr/sbin/munin08:19:403
390099753,26cyclictest4321-21latency_hist11:04:133
390099752,68cyclictest638-21runrttasks10:33:033
390099752,68cyclictest1519-21ssh10:17:053
390099752,67cyclictest14752-21ssh10:34:323
390099752,66cyclictest25118-21/usr/sbin/munin07:24:323
390099742,36cyclictest2105-21/usr/sbin/munin07:49:423
390099713,26cyclictest0-21swapper/310:55:503
390099712,63cyclictest19483-21/usr/sbin/munin07:09:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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