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2026-03-01 - 14:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 28, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1601399632,7cyclictest30642-21sshd07:03:390
16024995910,5cyclictest0-21swapper/209:52:292
16013995920,34cyclictest3-21ksoftirqd/010:58:080
16013995920,34cyclictest3-21ksoftirqd/010:58:080
1602499575,46cyclictest0-21swapper/211:15:072
1553825710,17sleep20-21swapper/206:25:232
1602499565,45cyclictest0-21swapper/211:41:382
1602499565,45cyclictest0-21swapper/211:41:382
1601799565,5cyclictest0-21swapper/110:51:381
1601799564,46cyclictest0-21swapper/111:44:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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