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2026-01-23 - 19:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 23, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26833997323,44cyclictest11904-21/usr/sbin/munin07:32:572
26833997122,43cyclictest638-21runrttasks09:24:112
26833997122,43cyclictest638-21runrttasks09:24:112
26833997122,43cyclictest26924-21/usr/sbin/munin08:12:532
26833997122,42cyclictest8617-21if_eth207:22:492
26833997121,44cyclictest6281-21/usr/sbin/munin07:17:562
26833997022,42cyclictest638-21runrttasks10:15:262
26833997022,42cyclictest18470-21switchtime07:48:002
26833997019,44cyclictest6312-21ssh11:44:262
26833997019,44cyclictest6312-21ssh11:44:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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