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2026-03-04 - 14:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Wed Mar 04, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2523326011,18sleep30-21swapper/318:24:483
2562399577,43cyclictest0-21swapper/321:27:573
2562399575,46cyclictest0-21swapper/320:57:273
2560099574,29cyclictest0-21swapper/021:01:490
2560099573,48cyclictest0-21swapper/018:47:280
2560099573,48cyclictest0-21swapper/018:47:280
2562399564,46cyclictest0-21swapper/320:45:283
2562399564,45cyclictest0-21swapper/320:51:183
72602550,3sleep227-21rcuc/220:26:432
2560099554,46cyclictest0-21swapper/019:01:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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