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2026-03-08 - 05:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot4.osadl.org (updated Sun Mar 08, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1821099692,61cyclictest18657-21fschecks_time18:24:182
1821099623,7cyclictest1125-21/usr/sbin/munin23:19:282
1821599596,47cyclictest0-21swapper/321:03:083
1821599584,7cyclictest0-21swapper/323:05:263
1820399575,8cyclictest0-21swapper/121:35:081
1821599564,46cyclictest0-21swapper/320:58:393
1821599554,45cyclictest0-21swapper/323:15:233
1821599554,45cyclictest0-21swapper/322:35:363
1821599553,46cyclictest0-21swapper/321:58:573
1820399554,45cyclictest0-21swapper/122:18:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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