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2026-02-10 - 15:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Tue Feb 10, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1295799614,51cyclictest29-21ksoftirqd/210:02:502
1294599614,31cyclictest0-21swapper/008:52:520
1294599605,48cyclictest0-21swapper/010:29:080
1294599584,9cyclictest0-21swapper/009:03:180
1295799575,46cyclictest0-21swapper/211:48:062
1294999565,45cyclictest0-21swapper/111:08:171
1294599564,46cyclictest0-21swapper/011:41:470
1294599564,46cyclictest0-21swapper/010:14:290
1294599554,45cyclictest0-21swapper/009:19:350
1295799544,43cyclictest0-21swapper/211:53:082
1295799543,44cyclictest0-21swapper/209:15:032
1294599544,44cyclictest0-21swapper/010:07:250
1294599543,6cyclictest6689-21ssh10:22:480
1294599543,46cyclictest0-21swapper/011:13:030
1294599543,46cyclictest0-21swapper/010:52:060
1294599535,43cyclictest0-21swapper/011:12:010
1294599534,44cyclictest0-21swapper/011:55:490
1294599534,43cyclictest0-21swapper/009:43:560
1295799526,38cyclictest0-21swapper/210:18:152
1295799524,42cyclictest0-21swapper/211:47:462
1295799524,42cyclictest0-21swapper/211:47:462
1294999524,42cyclictest0-21swapper/111:31:501
1294599528,39cyclictest0-21swapper/010:39:180
1294599524,6cyclictest0-21swapper/009:29:500
1294599524,42cyclictest0-21swapper/010:23:480
1294599523,44cyclictest0-21swapper/011:46:480
1294599523,44cyclictest0-21swapper/011:46:480
1294599523,43cyclictest0-21swapper/009:08:100
1294599523,43cyclictest0-21swapper/009:08:100
1295799515,39cyclictest0-21swapper/210:33:152
1295799514,41cyclictest0-21swapper/208:28:192
12957995114,32cyclictest10711-21sshd07:55:052
1294999514,41cyclictest0-21swapper/111:59:561
1294999513,15cyclictest0-21swapper/107:32:061
1294599514,41cyclictest0-21swapper/008:41:320
1294599513,44cyclictest0-21swapper/010:58:020
1294599513,44cyclictest0-21swapper/010:11:290
124362519,36sleep30-21swapper/306:34:393
1296199504,40cyclictest0-21swapper/310:25:283
12961995018,26cyclictest25976-21diskmemload09:22:273
1295799505,39cyclictest0-21swapper/211:13:172
12957995013,6cyclictest11101-21uptime09:43:202
1294599505,39cyclictest0-21swapper/011:22:540
1294599505,39cyclictest0-21swapper/009:13:570
1294599504,40cyclictest0-21swapper/008:56:490
1294599503,42cyclictest0-21swapper/011:48:350
1294599503,42cyclictest0-21swapper/009:27:000
12945995012,32cyclictest0-21swapper/008:58:390
1296199493,41cyclictest0-21swapper/307:38:183
1295799494,40cyclictest0-21swapper/208:33:072
1295799494,39cyclictest0-21swapper/207:03:162
1295799494,38cyclictest0-21swapper/210:46:092
1295799493,40cyclictest0-21swapper/208:41:062
1294999495,38cyclictest0-21swapper/106:38:231
1294599498,35cyclictest0-21swapper/011:05:310
1294599495,38cyclictest0-21swapper/008:45:390
1294599494,39cyclictest0-21swapper/010:35:390
1294599494,39cyclictest0-21swapper/009:59:270
1294599494,39cyclictest0-21swapper/009:40:320
1294599493,7cyclictest0-21swapper/010:53:390
1294599493,7cyclictest0-21swapper/010:53:390
12945994912,5cyclictest0-21swapper/011:31:350
12945994912,5cyclictest0-21swapper/009:54:330
1296199489,34cyclictest0-21swapper/311:09:343
1296199484,38cyclictest0-21swapper/310:40:053
1295799488,34cyclictest0-21swapper/209:30:362
1295799486,37cyclictest0-21swapper/210:09:132
1295799486,37cyclictest0-21swapper/209:20:062
1295799486,36cyclictest0-21swapper/210:39:202
1295799486,36cyclictest0-21swapper/210:14:142
1295799484,8cyclictest0-21swapper/209:39:492
1295799484,39cyclictest0-21swapper/209:49:032
1295799484,38cyclictest0-21swapper/212:07:332
1295799484,38cyclictest0-21swapper/211:35:472
1295799484,38cyclictest0-21swapper/211:28:502
1295799484,38cyclictest0-21swapper/211:08:542
12957994831,11cyclictest0-21swapper/208:54:302
1295799483,40cyclictest0-21swapper/208:23:162
1295799483,39cyclictest0-21swapper/211:37:592
1295799482,40cyclictest9864-21kworker/2:110:30:382
12957994814,29cyclictest30077-21sshd08:43:042
12957994811,31cyclictest0-21swapper/211:04:152
12957994811,31cyclictest0-21swapper/207:23:272
1295799481,42cyclictest3682-21ssh08:50:302
1294999484,38cyclictest0-21swapper/110:19:511
12949994816,27cyclictest25976-21diskmemload11:03:301
1294599487,35cyclictest0-21swapper/011:33:150
1294599484,38cyclictest0-21swapper/011:58:320
1294599484,38cyclictest0-21swapper/011:18:280
1294599483,40cyclictest0-21swapper/009:35:390
1294599483,39cyclictest0-21swapper/012:03:180
1296199475,37cyclictest0-21swapper/311:22:183
1296199474,39cyclictest0-21swapper/310:17:583
12961994738,5cyclictest37-21ksoftirqd/309:07:513
1296199473,40cyclictest0-21swapper/311:49:163
1296199471,4cyclictest32699-21ssh09:29:003
1295799478,33cyclictest0-21swapper/210:24:092
1295799478,33cyclictest0-21swapper/209:10:592
1295799478,33cyclictest0-21swapper/209:10:592
1295799476,36cyclictest0-21swapper/210:49:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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