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2026-01-20 - 20:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 20, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1445699684,58cyclictest0-21swapper/209:31:152
1445699623,54cyclictest0-21swapper/207:04:102
1445699613,52cyclictest0-21swapper/209:59:072
1445699613,52cyclictest0-21swapper/208:54:152
1445699594,50cyclictest0-21swapper/210:45:322
14450995811,41cyclictest0-21swapper/112:13:081
1445699577,5cyclictest0-21swapper/211:55:532
1445699574,47cyclictest0-21swapper/210:26:552
1445699573,48cyclictest28709-21ssh11:41:232
1444699575,45cyclictest0-21swapper/009:25:460
1444699575,45cyclictest0-21swapper/009:25:460
1445699564,47cyclictest0-21swapper/211:35:362
1445699554,45cyclictest0-21swapper/211:17:122
1445699554,45cyclictest0-21swapper/211:08:182
1445699554,45cyclictest0-21swapper/209:38:022
1445699553,47cyclictest0-21swapper/210:23:112
14461995445,5cyclictest37-21ksoftirqd/312:09:033
1446199542,7cyclictest29840-21sed09:34:263
1445699542,7cyclictest3136-21sshd11:49:462
1445099544,44cyclictest0-21swapper/109:07:371
1444699544,9cyclictest0-21swapper/006:54:310
1446199534,43cyclictest0-21swapper/309:17:083
1446199534,11cyclictest0-21swapper/310:49:543
1446199534,11cyclictest0-21swapper/310:49:543
1445699534,43cyclictest0-21swapper/211:27:232
1445699533,44cyclictest0-21swapper/212:05:202
1446199523,8cyclictest0-21swapper/310:24:253
1444699524,42cyclictest0-21swapper/008:58:170
1444699524,41cyclictest0-21swapper/011:21:340
14446995214,6cyclictest10490-21unixbench-2d11:59:350
1445699515,41cyclictest0-21swapper/210:41:352
1445699514,41cyclictest0-21swapper/212:19:032
1445699514,41cyclictest0-21swapper/209:18:132
14456995115,31cyclictest7784-21sshd10:30:322
14456995111,34cyclictest0-21swapper/210:16:562
1445099514,40cyclictest0-21swapper/111:49:351
1444699513,43cyclictest0-21swapper/011:28:300
1446199504,41cyclictest0-21swapper/309:02:473
1446199504,40cyclictest0-21swapper/310:07:153
1446199504,40cyclictest0-21swapper/310:07:153
1446199503,42cyclictest0-21swapper/311:17:243
1445699506,38cyclictest0-21swapper/209:43:582
1445699505,39cyclictest0-21swapper/209:28:292
1445699505,39cyclictest0-21swapper/209:28:292
1445699504,8cyclictest0-21swapper/212:13:222
1445699504,40cyclictest0-21swapper/210:36:452
1445699504,40cyclictest0-21swapper/208:09:312
1445699504,39cyclictest0-21swapper/212:00:082
1445699503,41cyclictest0-21swapper/209:50:552
1445699503,13cyclictest29182-21wc07:24:382
14456995012,32cyclictest0-21swapper/211:46:452
14456995012,32cyclictest0-21swapper/209:04:512
14456995011,33cyclictest0-21swapper/210:51:172
14456995011,33cyclictest0-21swapper/210:51:172
14450995010,34cyclictest0-21swapper/110:14:481
1444699504,40cyclictest0-21swapper/010:11:350
1444699503,41cyclictest0-21swapper/010:22:050
14446995018,27cyclictest27469-21diskmemload09:42:540
1446199495,11cyclictest0-21swapper/309:09:173
14461994911,5cyclictest0-21swapper/310:48:313
1445699496,38cyclictest0-21swapper/210:02:412
1445699496,37cyclictest0-21swapper/209:10:322
1445699495,39cyclictest0-21swapper/211:01:222
1445699494,39cyclictest0-21swapper/210:04:202
1445699494,39cyclictest0-21swapper/210:04:202
1445699494,39cyclictest0-21swapper/207:54:312
1445699493,40cyclictest565-21irqbalance09:00:472
1445699493,40cyclictest0-21swapper/210:11:452
1445099494,39cyclictest0-21swapper/110:19:531
1444699494,39cyclictest0-21swapper/010:41:400
1444699492,41cyclictest6313-21kworker/0:212:14:320
14446994910,34cyclictest0-21swapper/010:09:060
14446994910,34cyclictest0-21swapper/010:09:060
1446199484,38cyclictest0-21swapper/312:01:113
1446199484,38cyclictest0-21swapper/311:13:553
1446199484,38cyclictest0-21swapper/309:45:133
1446199483,39cyclictest0-21swapper/311:36:333
14461994816,26cyclictest18043-21cpu09:19:193
1445699488,34cyclictest0-21swapper/210:58:402
1445699487,34cyclictest0-21swapper/209:44:402
1445699486,37cyclictest0-21swapper/208:52:122
1445699485,37cyclictest0-21swapper/211:23:152
1445699484,38cyclictest0-21swapper/211:32:132
1445699484,38cyclictest0-21swapper/209:19:502
1445699484,38cyclictest0-21swapper/208:44:242
1445699484,38cyclictest0-21swapper/207:34:412
1445699484,38cyclictest0-21swapper/207:19:242
1445699484,38cyclictest0-21swapper/207:04:272
1445699483,39cyclictest0-21swapper/208:39:302
1445699483,39cyclictest0-21swapper/207:09:342
14456994810,32cyclictest0-21swapper/211:09:252
1445099485,36cyclictest0-21swapper/111:32:461
1445099484,38cyclictest0-21swapper/110:34:341
1445099483,39cyclictest0-21swapper/109:59:251
14450994812,30cyclictest0-21swapper/112:08:561
1444699485,37cyclictest0-21swapper/010:14:080
1444699484,39cyclictest0-21swapper/012:07:100
1444699484,39cyclictest0-21swapper/011:39:310
1444699484,38cyclictest0-21swapper/010:00:250
14446994816,6cyclictest27469-21diskmemload09:53:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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