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2026-01-30 - 18:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 30, 2026 12:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1240925912,17sleep20-21swapper/206:43:212
1268899583,29cyclictest563-21sshd08:53:270
1269299574,47cyclictest0-21swapper/108:45:551
1270699565,44cyclictest0-21swapper/312:05:303
1270699553,46cyclictest0-21swapper/311:37:113
1269299554,44cyclictest0-21swapper/110:15:531
1270699543,45cyclictest0-21swapper/307:09:063
1270699543,45cyclictest0-21swapper/307:09:063
1268899542,46cyclictest8171-21munin-run09:03:450
1270699534,7cyclictest0-21swapper/310:19:433
1269299534,43cyclictest0-21swapper/109:00:151
1269299533,46cyclictest0-21swapper/107:29:081
1269299532,45cyclictest4227-21ssh09:40:511
12688995316,32cyclictest23284-21needreboot10:49:030
12688995316,32cyclictest23284-21needreboot10:49:030
1270699524,41cyclictest0-21swapper/310:57:523
1270699523,43cyclictest37-21ksoftirqd/310:01:233
1269299524,43cyclictest0-21swapper/112:03:221
1269299524,43cyclictest0-21swapper/109:32:041
1269299524,43cyclictest0-21swapper/109:32:041
1269299524,42cyclictest0-21swapper/111:37:011
1268899524,6cyclictest0-21swapper/010:35:530
1270699516,41cyclictest0-21swapper/309:12:143
1270699514,42cyclictest0-21swapper/309:31:343
1270699514,42cyclictest0-21swapper/309:31:343
12706995113,32cyclictest28685-21sshd08:47:073
1269299515,40cyclictest0-21swapper/110:03:211
1269299513,43cyclictest0-21swapper/112:12:201
1269299513,42cyclictest0-21swapper/110:34:231
1268899514,41cyclictest0-21swapper/010:43:300
1268899514,22cyclictest0-21swapper/011:30:260
1268899513,43cyclictest0-21swapper/010:45:220
1268899513,42cyclictest0-21swapper/011:40:570
1268899513,42cyclictest0-21swapper/011:40:570
12688995114,32cyclictest0-21swapper/011:33:540
12688995111,34cyclictest0-21swapper/009:07:590
1270699509,35cyclictest0-21swapper/309:35:493
1270699505,38cyclictest0-21swapper/306:43:553
1270699502,43cyclictest12707-21ssh10:34:323
1269299505,40cyclictest0-21swapper/109:11:161
1269299504,41cyclictest0-21swapper/109:27:351
1269299504,40cyclictest0-21swapper/111:09:361
1269299504,40cyclictest0-21swapper/109:04:251
1269299504,39cyclictest0-21swapper/111:51:511
1269299502,42cyclictest9352-21ssh11:56:201
1269299501,44cyclictest30144-21kworker/1:211:23:181
1268899504,39cyclictest0-21swapper/009:29:580
1268899504,39cyclictest0-21swapper/009:29:580
1268899503,43cyclictest0-21swapper/007:24:200
1268899503,42cyclictest0-21swapper/011:14:190
1268899503,41cyclictest0-21swapper/009:37:340
1268899502,42cyclictest13236-21/usr/sbin/munin09:53:570
12688995018,7cyclictest2626-21interrupts09:39:010
1270699496,37cyclictest0-21swapper/309:55:353
1270699495,38cyclictest0-21swapper/312:09:043
1270699494,8cyclictest0-21swapper/311:05:123
1270699494,40cyclictest0-21swapper/310:59:323
1270699494,40cyclictest0-21swapper/307:39:093
1270699494,39cyclictest0-21swapper/311:53:113
1270699494,39cyclictest0-21swapper/310:40:423
1270699494,39cyclictest0-21swapper/309:19:113
1270699493,41cyclictest0-21swapper/310:52:123
1270699493,41cyclictest0-21swapper/310:52:123
1270699493,40cyclictest0-21swapper/310:27:233
12706994912,31cyclictest0-21swapper/308:49:443
12706994911,5cyclictest0-21swapper/309:50:113
12706994910,33cyclictest0-21swapper/310:43:553
1269299495,38cyclictest0-21swapper/108:57:411
1269299494,39cyclictest0-21swapper/110:40:061
1269299493,41cyclictest0-21swapper/110:28:531
1269299493,40cyclictest0-21swapper/109:37:071
12692994913,31cyclictest31940-21sshd08:51:071
1268899494,39cyclictest0-21swapper/008:43:480
1268899494,39cyclictest0-21swapper/008:23:590
1268899493,42cyclictest0-21swapper/010:17:230
12688994917,26cyclictest25707-21diskmemload09:15:460
12688994911,6cyclictest0-21swapper/009:20:130
1270699486,37cyclictest0-21swapper/311:22:053
1270699486,37cyclictest0-21swapper/309:26:413
1270699485,37cyclictest0-21swapper/311:59:013
1270699485,37cyclictest0-21swapper/311:44:283
1270699485,37cyclictest0-21swapper/311:24:203
1270699484,39cyclictest0-21swapper/308:03:573
1270699484,38cyclictest0-21swapper/311:11:033
1270699484,38cyclictest0-21swapper/310:29:173
1270699484,38cyclictest0-21swapper/308:03:463
1270699484,37cyclictest0-21swapper/307:26:443
1270699483,40cyclictest0-21swapper/310:17:133
1270699483,40cyclictest0-21swapper/310:08:133
1270699483,39cyclictest0-21swapper/307:54:013
1269299488,34cyclictest0-21swapper/110:51:501
1269299488,34cyclictest0-21swapper/110:51:501
1269299488,34cyclictest0-21swapper/109:44:151
1269299484,39cyclictest0-21swapper/109:48:541
1269299484,38cyclictest0-21swapper/112:05:111
1269299484,38cyclictest0-21swapper/111:04:111
1269299484,38cyclictest0-21swapper/111:00:551
1269299484,38cyclictest0-21swapper/110:55:461
1269299484,38cyclictest0-21swapper/110:44:241
1269299484,38cyclictest0-21swapper/109:55:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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