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2026-01-26 - 23:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Mon Jan 26, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12755997610,6cyclictest0-21swapper/311:28:143
1275599758,7cyclictest0-21swapper/311:21:283
1275599746,61cyclictest0-21swapper/308:59:013
1275599742,66cyclictest29500-21sed11:41:203
1275599736,60cyclictest0-21swapper/309:26:313
1275599734,7cyclictest0-21swapper/311:20:323
1275599734,18cyclictest0-21swapper/309:08:133
1275599732,66cyclictest20045-21ssh10:04:263
1275599725,7cyclictest0-21swapper/311:11:533
1275599725,60cyclictest0-21swapper/310:32:463
1275599725,60cyclictest0-21swapper/309:35:423
1275599724,9cyclictest0-21swapper/311:58:473
1275599724,7cyclictest0-21swapper/312:02:213
1275599715,60cyclictest0-21swapper/310:26:133
1275599715,6cyclictest0-21swapper/310:59:403
1275599715,59cyclictest0-21swapper/310:54:223
1275599715,59cyclictest0-21swapper/310:54:223
1275599714,7cyclictest0-21swapper/310:00:143
1275599714,60cyclictest0-21swapper/311:04:343
1275599714,6cyclictest0-21swapper/312:13:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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