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2026-01-21 - 01:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 20, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1445699684,58cyclictest0-21swapper/209:31:152
1445699623,54cyclictest0-21swapper/207:04:102
1445699613,52cyclictest0-21swapper/209:59:072
1445699613,52cyclictest0-21swapper/208:54:152
1445699594,50cyclictest0-21swapper/210:45:322
14450995811,41cyclictest0-21swapper/112:13:081
1445699577,5cyclictest0-21swapper/211:55:532
1445699574,47cyclictest0-21swapper/210:26:552
1445699573,48cyclictest28709-21ssh11:41:232
1444699575,45cyclictest0-21swapper/009:25:460
1444699575,45cyclictest0-21swapper/009:25:460
1445699564,47cyclictest0-21swapper/211:35:362
1445699554,45cyclictest0-21swapper/211:17:122
1445699554,45cyclictest0-21swapper/211:08:182
1445699554,45cyclictest0-21swapper/209:38:022
1445699553,47cyclictest0-21swapper/210:23:112
14461995445,5cyclictest37-21ksoftirqd/312:09:033
1446199542,7cyclictest29840-21sed09:34:263
1445699542,7cyclictest3136-21sshd11:49:462
1445099544,44cyclictest0-21swapper/109:07:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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