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2026-02-09 - 00:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sun Feb 08, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2623126211,17sleep20-21swapper/206:35:132
2680099573,8cyclictest0-21swapper/306:52:133
2678099574,47cyclictest0-21swapper/009:27:140
2680099564,45cyclictest0-21swapper/311:25:313
2678099565,45cyclictest0-21swapper/011:29:410
2680099554,46cyclictest0-21swapper/311:53:523
2680099554,46cyclictest0-21swapper/310:20:323
2680099554,45cyclictest0-21swapper/309:23:243
2678099554,45cyclictest0-21swapper/009:23:470
2680099544,44cyclictest0-21swapper/309:54:033
2680099544,44cyclictest0-21swapper/309:35:423
2678099543,46cyclictest0-21swapper/012:02:300
2678099534,17cyclictest0-21swapper/010:20:560
26780995313,33cyclictest21195-21latency_hist07:48:570
26780995310,37cyclictest0-21swapper/010:50:320
2680099527,39cyclictest0-21swapper/311:13:423
2680099525,41cyclictest0-21swapper/311:01:413
2680099525,41cyclictest0-21swapper/309:16:243
2680099522,45cyclictest4232-21ssh09:59:433
26800995217,7cyclictest5402-21sshd11:29:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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