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2026-02-27 - 06:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Fri Feb 27, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2048321000,4sleep120484-21sh21:28:511
2784199633,55cyclictest0-21swapper/320:49:303
2783699604,49cyclictest0-21swapper/220:44:512
2784199594,49cyclictest0-21swapper/320:44:013
2784199575,29cyclictest0-21swapper/321:49:083
2784199574,47cyclictest0-21swapper/322:38:393
2784199574,16cyclictest0-21swapper/320:44:493
2784199573,47cyclictest22804-21iostat_ios19:39:203
2784199572,7cyclictest22758-21latency_hist22:58:573
2784199564,6cyclictest0-21swapper/319:39:013
2783699564,7cyclictest0-21swapper/222:45:362
2783699554,45cyclictest0-21swapper/220:43:312
2783699554,44cyclictest0-21swapper/222:53:562
2783699553,47cyclictest0-21swapper/223:48:072
2783099555,7cyclictest0-21swapper/121:59:371
2784199544,45cyclictest0-21swapper/323:07:463
2784199544,44cyclictest0-21swapper/321:22:573
2784199543,46cyclictest0-21swapper/322:08:373
2784199542,6cyclictest2733-21ssh22:31:033
2783699546,41cyclictest0-21swapper/220:29:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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