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2026-01-20 - 13:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 20, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2267699653,56cyclictest0-21swapper/321:09:243
2267699574,47cyclictest0-21swapper/321:22:523
2267699573,27cyclictest8112-21sshd23:47:533
22676995641,10cyclictest0-21swapper/322:39:213
2267699564,46cyclictest0-21swapper/323:33:193
2267699564,46cyclictest0-21swapper/323:33:193
2267699564,46cyclictest0-21swapper/322:48:543
2265699564,7cyclictest0-21swapper/000:04:190
2219525612,38sleep30-21swapper/318:46:463
2267699553,46cyclictest0-21swapper/323:09:503
2267699552,47cyclictest31160-21ssh00:18:383
2265699554,44cyclictest0-21swapper/022:29:010
2267699546,41cyclictest0-21swapper/321:24:493
2267699543,46cyclictest0-21swapper/319:03:523
22676995417,31cyclictest31742-21sshd22:09:493
22676995417,31cyclictest31742-21sshd22:09:493
2265699545,43cyclictest0-21swapper/023:25:500
2265699544,44cyclictest0-21swapper/023:19:500
2265699543,45cyclictest0-21swapper/021:24:170
22656995414,7cyclictest8367-21cat19:34:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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