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2026-01-31 - 18:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sat Jan 31, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1923599593,49cyclictest23037-21unixbench-2d12:03:402
1922699593,51cyclictest0-21swapper/107:18:151
19222995950,5cyclictest3-21ksoftirqd/006:53:160
19235995810,42cyclictest0-21swapper/209:45:532
1924299577,43cyclictest0-21swapper/311:39:313
1924299577,43cyclictest0-21swapper/311:39:313
1923599576,45cyclictest26826-21/usr/sbin/munin08:28:392
1922699574,48cyclictest0-21swapper/108:53:141
1923599569,5cyclictest16780-21kworker/2:008:58:332
1898025610,16sleep10-21swapper/106:43:131
1923599557,42cyclictest21710-21/usr/sbin/munin06:48:332
1923599555,44cyclictest15572-21/usr/sbin/munin07:58:362
1923599554,7cyclictest0-21swapper/211:32:492
19235995414,34cyclictest13560-21ssh11:52:292
19235995413,35cyclictest8880-21ssh11:45:372
19235995413,35cyclictest19784-21ssh11:59:312
1922299544,45cyclictest0-21swapper/011:28:220
1924299534,43cyclictest0-21swapper/309:44:113
1923599537,40cyclictest19970-21ls09:08:402
1923599537,40cyclictest19970-21ls09:08:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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