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2026-01-30 - 03:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 30, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2408599764,38cyclictest0-21swapper/322:44:203
2408599764,38cyclictest0-21swapper/322:44:203
24085997511,31cyclictest0-21swapper/322:55:303
2408599745,39cyclictest0-21swapper/322:04:193
2408599734,39cyclictest0-21swapper/321:58:063
2408599724,41cyclictest0-21swapper/322:52:543
2408599714,39cyclictest0-21swapper/323:57:453
2408599714,39cyclictest0-21swapper/323:57:453
2407899715,7cyclictest0-21swapper/222:24:112
2408599702,39cyclictest28721-21ssh00:05:273
2407899705,33cyclictest0-21swapper/223:41:572
2408599693,39cyclictest0-21swapper/319:09:333
2407899695,13cyclictest0-21swapper/221:17:172
2407899695,13cyclictest0-21swapper/221:17:172
2408599682,5cyclictest31292-21ls00:09:163
2407899685,31cyclictest0-21swapper/223:28:032
2407899668,27cyclictest0-21swapper/222:11:392
2407899665,7cyclictest0-21swapper/221:10:522
2407899665,7cyclictest0-21swapper/221:10:522
2407899664,32cyclictest0-21swapper/200:05:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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