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2026-02-10 - 05:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Tue Feb 10, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2170499717,57cyclictest28284-21sshd23:20:482
2170499681,61cyclictest0-21swapper/222:08:072
21704996210,46cyclictest0-21swapper/220:59:362
2170499611,54cyclictest0-21swapper/220:39:172
21704996013,41cyclictest21488-21basename21:03:162
21695996026,28cyclictest28618-21tr18:53:300
21695996026,28cyclictest28618-21tr18:53:300
2170499597,46cyclictest543-21systemd-logind21:58:062
2170499595,47cyclictest32097-21ssh23:25:462
21704995713,38cyclictest2337-21diskmemload23:02:502
21704995713,37cyclictest29034-21ssh21:13:122
21704995642,10cyclictest0-21swapper/222:19:252
21704995642,10cyclictest0-21swapper/222:19:252
2170499564,46cyclictest0-21swapper/222:33:462
21695995617,33cyclictest22171-21/usr/sbin/munin23:13:140
21695995617,33cyclictest22171-21/usr/sbin/munin23:13:140
2170499554,45cyclictest0-21swapper/220:43:272
2170499553,46cyclictest0-21swapper/221:19:112
21704995513,36cyclictest10644-21mailstats22:13:322
21695995518,31cyclictest23217-21aten_rbpower_po21:48:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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