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2026-01-26 - 11:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Mon Jan 26, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26409996657,5cyclictest29-21ksoftirqd/222:31:082
45642640,7sleep30-21swapper/322:08:423
26400996254,4cyclictest21-21ksoftirqd/120:56:101
2640999605,48cyclictest0-21swapper/221:14:292
26417995911,41cyclictest27904-21sendmail_mailtr18:46:393
2640999588,44cyclictest4644-21latency_hist21:26:112
2640999588,44cyclictest4644-21latency_hist21:26:112
2641799575,44cyclictest0-21swapper/322:36:293
2640999574,47cyclictest0-21swapper/221:32:192
2641799564,46cyclictest0-21swapper/323:50:163
26417995610,39cyclictest31220-21taskset22:01:253
2641799554,44cyclictest0-21swapper/322:17:043
26417995512,36cyclictest28879-21/usr/sbin/munin18:51:383
26417995512,36cyclictest28879-21/usr/sbin/munin18:51:383
2640999556,44cyclictest0-21swapper/223:25:572
2641799542,46cyclictest0-21swapper/323:08:573
2640999543,46cyclictest0-21swapper/222:46:572
26417995310,37cyclictest549-21ls22:46:233
2640999534,12cyclictest0-21swapper/221:01:402
2640999532,46cyclictest31321-21ssh21:17:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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