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2026-02-20 - 05:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Fri Feb 20, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1182599748,7cyclictest0-21swapper/322:40:153
1182599728,58cyclictest0-21swapper/321:12:053
1182599724,62cyclictest0-21swapper/322:23:323
11825997212,5cyclictest0-21swapper/322:14:453
1182599719,55cyclictest0-21swapper/321:04:093
1182599715,59cyclictest0-21swapper/323:35:573
1182599715,59cyclictest0-21swapper/323:35:573
1182599715,59cyclictest0-21swapper/320:49:033
11825997110,55cyclictest0-21swapper/322:50:463
11825997110,5cyclictest0-21swapper/320:41:043
1182599706,58cyclictest0-21swapper/320:34:213
1182599706,58cyclictest0-21swapper/320:34:213
1182599705,7cyclictest0-21swapper/323:23:523
1182599705,7cyclictest0-21swapper/322:22:143
1182599705,7cyclictest0-21swapper/322:22:143
1182599705,59cyclictest0-21swapper/322:28:303
1182599705,58cyclictest0-21swapper/321:39:493
1182599704,7cyclictest0-21swapper/321:52:523
1182599704,7cyclictest0-21swapper/321:20:153
11825997010,53cyclictest0-21swapper/321:23:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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