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2026-01-29 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Thu Jan 29, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1933221690,2sleep229-21ksoftirqd/200:04:492
1738699623,54cyclictest0-21swapper/019:05:220
1740799613,52cyclictest0-21swapper/323:09:503
1738699608,46cyclictest0-21swapper/021:46:170
1738699595,47cyclictest0-21swapper/021:28:520
1738699568,43cyclictest0-21swapper/020:59:280
1738699564,47cyclictest0-21swapper/020:44:430
1738699564,46cyclictest0-21swapper/021:13:330
1738699564,46cyclictest0-21swapper/021:13:330
1740799556,43cyclictest0-21swapper/323:06:053
1740799554,45cyclictest0-21swapper/300:08:093
1738699554,45cyclictest0-21swapper/000:14:080
1738699554,44cyclictest0-21swapper/020:52:530
1740799542,46cyclictest3451-21ssh22:18:153
1738699544,17cyclictest0-21swapper/023:09:300
1738699543,46cyclictest0-21swapper/023:31:570
1697825410,16sleep10-21swapper/118:42:321
1740799536,41cyclictest0-21swapper/322:34:513
1740799534,6cyclictest0-21swapper/323:48:293
1740799534,43cyclictest0-21swapper/323:20:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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