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2026-01-27 - 03:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 27, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2334099816,43cyclictest0-21swapper/222:23:562
2333199585,46cyclictest0-21swapper/122:17:061
2334099565,45cyclictest0-21swapper/223:19:142
2334099564,46cyclictest0-21swapper/221:31:572
2333199564,45cyclictest0-21swapper/120:49:381
2332799564,47cyclictest0-21swapper/018:47:510
2334099554,45cyclictest0-21swapper/223:56:532
2334099544,6cyclictest0-21swapper/223:28:342
2334099534,7cyclictest0-21swapper/223:39:242
2334099534,43cyclictest0-21swapper/223:31:342
2334099534,24cyclictest0-21swapper/222:17:112
23340995312,9cyclictest0-21swapper/219:05:582
2333199537,16cyclictest0-21swapper/121:29:331
2333199533,17cyclictest0-21swapper/120:15:581
227542537,16sleep10-21swapper/118:41:401
2334599528,37cyclictest6194-21grep22:56:083
2334599524,42cyclictest0-21swapper/300:11:033
2334099522,7cyclictest23832-21/usr/sbin/munin23:20:452
2334099522,45cyclictest17973-21ssh22:30:362
2333199525,16cyclictest0-21swapper/123:46:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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