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2026-02-08 - 03:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sun Feb 08, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
375099623,9cyclictest2085-21sshd22:27:222
375099623,9cyclictest2085-21sshd22:27:222
375099584,48cyclictest0-21swapper/221:19:162
374299575,45cyclictest0-21swapper/122:50:481
375099564,46cyclictest0-21swapper/221:30:402
375099562,4cyclictest16771-21diskmemload23:11:502
374299564,47cyclictest0-21swapper/123:20:281
3756995526,23cyclictest16043-21sed21:19:403
3756995517,32cyclictest554-21dbus-daemon20:39:123
375099554,7cyclictest0-21swapper/223:40:372
375099554,7cyclictest0-21swapper/223:40:372
375099554,7cyclictest0-21swapper/223:03:582
375099554,44cyclictest0-21swapper/223:36:482
3756995421,28cyclictest29164-21grep23:44:383
3756995417,31cyclictest543-21systemd-logind20:09:123
3756995417,31cyclictest11494-21idleruntime21:14:273
375099544,44cyclictest0-21swapper/221:04:472
375099543,5cyclictest0-21swapper/223:04:582
375099543,28cyclictest0-21swapper/221:54:482
375099541,48cyclictest20087-21latency_hist23:34:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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