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2026-01-25 - 09:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sun Jan 25, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324032650,6sleep032408-21unixbench_singl19:27:150
1504425910,42sleep20-21swapper/218:43:172
1504425910,42sleep20-21swapper/218:43:172
1557099573,48cyclictest0-21swapper/022:20:410
1557499564,46cyclictest0-21swapper/121:54:311
1559199553,47cyclictest0-21swapper/319:32:523
1557499552,47cyclictest23911-21ssh23:32:271
1557099554,7cyclictest0-21swapper/023:47:030
1557099554,45cyclictest0-21swapper/023:07:360
1557099554,45cyclictest0-21swapper/000:08:090
1557099554,45cyclictest0-21swapper/000:08:090
1558399544,44cyclictest0-21swapper/223:13:592
1557499543,7cyclictest10765-21ssh23:58:481
15570995415,34cyclictest29570-21latency_hist23:41:400
1558399533,44cyclictest24067-21ssh21:22:212
1558399532,45cyclictest9757-21timerandwakeup23:57:082
1557499536,41cyclictest0-21swapper/122:36:371
1557099534,45cyclictest0-21swapper/020:26:490
1557099534,45cyclictest0-21swapper/020:26:490
1557099534,43cyclictest0-21swapper/021:31:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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