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2026-03-06 - 06:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Fri Mar 06, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
690399703,60cyclictest0-21swapper/122:15:411
690399663,57cyclictest4902-21open_inodes22:55:351
690399655,54cyclictest0-21swapper/120:25:471
690399654,55cyclictest0-21swapper/123:10:441
690399645,53cyclictest0-21swapper/121:50:501
690399633,7cyclictest24461-21ssh23:20:471
690399624,52cyclictest0-21swapper/122:25:381
690399614,6cyclictest0-21swapper/123:35:491
690399614,6cyclictest0-21swapper/123:35:491
690399612,7cyclictest24040-21awk21:55:321
664626112,18sleep00-21swapper/018:25:050
690399603,5cyclictest0-21swapper/121:00:461
690399603,5cyclictest0-21swapper/121:00:461
691099574,7cyclictest0-21swapper/221:34:322
655925710,15sleep10-21swapper/118:24:021
691099564,46cyclictest0-21swapper/220:30:042
690399563,47cyclictest26402-21grep22:40:451
649225611,16sleep20-21swapper/218:23:142
691799554,45cyclictest0-21swapper/320:54:333
691099556,43cyclictest0-21swapper/220:48:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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