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2026-02-16 - 23:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 16, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3506996551,9cyclictest37-21ksoftirqd/309:24:373
350699573,48cyclictest0-21swapper/309:53:193
350699572,50cyclictest8407-21sshd08:10:083
350299574,46cyclictest0-21swapper/210:52:142
350699564,26cyclictest0-21swapper/309:59:413
350299563,47cyclictest0-21swapper/210:29:152
349099563,46cyclictest0-21swapper/011:34:580
350699554,45cyclictest0-21swapper/311:28:143
350699554,45cyclictest0-21swapper/311:28:143
350699554,45cyclictest0-21swapper/309:45:263
350299555,43cyclictest0-21swapper/209:21:362
350299554,45cyclictest0-21swapper/211:31:432
350699546,42cyclictest0-21swapper/310:07:153
350699545,43cyclictest0-21swapper/311:55:333
350699544,6cyclictest0-21swapper/308:46:473
350699544,44cyclictest0-21swapper/307:45:093
350699544,42cyclictest0-21swapper/308:54:473
350299544,44cyclictest0-21swapper/209:44:562
349099543,44cyclictest0-21swapper/009:50:110
350699535,42cyclictest0-21swapper/311:24:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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