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2026-02-07 - 20:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 07, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107332690,3sleep3361ktimersoftd/309:02:453
1199499633,6cyclictest0-21swapper/106:39:571
1200599573,48cyclictest0-21swapper/309:46:163
1200599562,48cyclictest32675-21sshd11:39:353
1199899566,43cyclictest0-21swapper/208:54:432
1199899564,45cyclictest0-21swapper/210:06:322
11994995626,25cyclictest8190-21uniq10:24:381
11994995614,36cyclictest6263-21tune2fs11:04:391
12005995514,35cyclictest3360-21timerwakeupswit10:59:543
1199899554,45cyclictest0-21swapper/210:34:152
11994995522,27cyclictest1389-21ls07:34:491
1199499552,47cyclictest29131-21grep10:09:401
1199499552,47cyclictest29131-21grep10:09:401
11994995518,32cyclictest26678-21ls07:14:581
11994995516,33cyclictest638-21runrttasks09:25:521
11994995514,35cyclictest4845-21ntpdc11:44:461
1198999554,26cyclictest0-21swapper/009:17:020
1199899544,45cyclictest0-21swapper/210:35:252
11994995417,31cyclictest18470-21ntp_offset08:19:511
1198999543,45cyclictest0-21swapper/012:09:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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