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2026-01-21 - 14:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Wed Jan 21, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82332990,3sleep2281ktimersoftd/223:28:282
3874997016,47cyclictest16145-21unixbench_singl21:29:222
3874996310,47cyclictest16892-21diskmemload23:22:272
387499626,50cyclictest6866-21kworker/2:222:44:292
3874996210,46cyclictest19626-21ssh23:43:272
387499617,8cyclictest30834-21ssh21:06:312
3874996113,41cyclictest13343-21/usr/sbin/munin20:39:172
3874996112,9cyclictest4210-21ssh21:57:302
3874996112,9cyclictest4210-21ssh21:57:302
387499608,46cyclictest6749-21ssh21:59:492
3874996013,40cyclictest17588-21/usr/sbin/munin19:24:192
3874996012,42cyclictest3171-21aten_rbpower_en22:39:002
3874996012,42cyclictest3171-21aten_rbpower_en22:39:002
3874995911,42cyclictest3971-21/usr/sbin/munin20:14:082
387499587,45cyclictest0-21swapper/222:50:162
3874995815,38cyclictest3921-21latency_hist20:13:532
3874995813,39cyclictest9594-21/usr/sbin/munin20:29:172
3874995813,39cyclictest30729-21/usr/sbin/munin19:59:182
3874995812,40cyclictest5847-21/usr/sbin/munin20:19:192
3874995810,42cyclictest6363-21ssh21:17:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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