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2026-02-09 - 03:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 09, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15646997429,12cyclictest0-21swapper/322:42:163
1564699734,34cyclictest0-21swapper/322:20:313
15646997311,55cyclictest0-21swapper/320:40:413
1564699728,30cyclictest0-21swapper/321:10:553
1564699725,33cyclictest0-21swapper/323:09:413
1564699725,33cyclictest0-21swapper/321:42:123
1564699724,9cyclictest0-21swapper/322:08:393
1564699724,9cyclictest0-21swapper/321:34:073
1564699724,7cyclictest0-21swapper/322:52:103
1564699723,9cyclictest0-21swapper/323:00:193
15646997229,11cyclictest0-21swapper/323:58:353
1564699715,7cyclictest0-21swapper/321:20:263
1564699715,33cyclictest0-21swapper/323:14:503
1564699715,33cyclictest0-21swapper/300:01:433
1564699714,7cyclictest0-21swapper/323:04:523
1564699714,6cyclictest0-21swapper/321:14:113
1564699714,34cyclictest0-21swapper/322:17:473
1564699714,33cyclictest0-21swapper/321:58:063
15646997132,7cyclictest0-21swapper/323:39:553
1564699706,7cyclictest0-21swapper/321:49:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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