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2026-01-18 - 01:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Sat Jan 17, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1488999814,45cyclictest0-21swapper/310:02:503
14884996555,5cyclictest29-21ksoftirqd/211:10:412
14884996224,7cyclictest26953-21grep10:15:572
14884996224,7cyclictest26953-21grep10:15:572
1488999593,30cyclictest0-21swapper/311:05:433
1488499589,8cyclictest0-21swapper/210:52:212
1488499574,47cyclictest0-21swapper/211:42:002
1488499564,46cyclictest0-21swapper/211:13:202
14889995516,6cyclictest18831-21/usr/sbin/munin12:15:503
1488499554,45cyclictest0-21swapper/211:04:152
1488499554,44cyclictest0-21swapper/210:04:422
1488999544,7cyclictest0-21swapper/309:26:133
1488999543,45cyclictest0-21swapper/309:01:173
1488499543,6cyclictest0-21swapper/211:56:002
1488499543,45cyclictest0-21swapper/208:45:562
1488499534,43cyclictest0-21swapper/210:00:422
1488499534,43cyclictest0-21swapper/209:20:232
1487599534,43cyclictest0-21swapper/110:26:411
1488999525,41cyclictest0-21swapper/310:31:413
1488999525,25cyclictest0-21swapper/309:45:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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