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2026-01-28 - 18:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot4.osadl.org (updated Wed Jan 28, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3093099693,8cyclictest0-21swapper/306:51:143
3093099693,8cyclictest0-21swapper/306:51:143
30930996110,45cyclictest0-21swapper/310:30:323
2900725811,16sleep10-21swapper/106:39:551
3093099564,46cyclictest0-21swapper/310:12:573
3093099563,46cyclictest14565-21ssh09:30:223
3092299564,15cyclictest0-21swapper/209:47:382
3092299554,45cyclictest0-21swapper/212:12:152
3092299554,45cyclictest0-21swapper/211:09:062
30910995514,6cyclictest5376-21aten_rbpower_cu10:44:580
3093099542,46cyclictest4749-21/usr/sbin/munin07:00:223
3092299544,45cyclictest0-21swapper/211:44:302
3092299544,43cyclictest0-21swapper/210:45:492
3092299544,43cyclictest0-21swapper/210:28:272
3091099544,24cyclictest0-21swapper/011:00:380
3091099544,24cyclictest0-21swapper/011:00:380
3093099536,41cyclictest0-21swapper/310:05:343
3093099534,43cyclictest0-21swapper/310:24:333
3093099533,44cyclictest0-21swapper/311:49:453
3093099533,44cyclictest0-21swapper/311:49:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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