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2026-02-23 - 20:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 23, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19510996656,5cyclictest21-21ksoftirqd/108:55:521
1951799597,46cyclictest0-21swapper/210:07:002
1898425911,16sleep10-21swapper/106:27:301
1951799584,48cyclictest0-21swapper/209:09:332
1919325712,16sleep30-21swapper/306:30:013
1951099564,45cyclictest0-21swapper/111:09:281
1951099554,7cyclictest0-21swapper/111:56:571
1951099554,45cyclictest0-21swapper/111:19:381
1951099554,44cyclictest0-21swapper/109:58:401
1951099544,44cyclictest0-21swapper/111:03:391
1951099543,46cyclictest0-21swapper/108:48:321
1950699544,44cyclictest0-21swapper/009:22:410
1950699542,46cyclictest6067-21ssh10:49:290
1951799534,43cyclictest0-21swapper/210:39:242
1951099534,43cyclictest0-21swapper/110:47:591
1951099533,44cyclictest0-21swapper/109:27:101
1950699534,44cyclictest0-21swapper/008:36:160
1951799524,43cyclictest0-21swapper/209:44:542
1951099523,44cyclictest0-21swapper/111:54:301
1950699524,42cyclictest0-21swapper/008:45:220
19506995212,12cyclictest0-21swapper/008:52:330
1951099515,41cyclictest0-21swapper/108:34:121
1951099514,41cyclictest0-21swapper/111:36:491
1951099513,43cyclictest0-21swapper/111:25:341
1951099513,43cyclictest0-21swapper/111:25:341
1950699515,40cyclictest0-21swapper/009:14:380
1950699514,42cyclictest0-21swapper/011:53:050
1950699513,10cyclictest0-21swapper/010:11:200
1951799504,41cyclictest0-21swapper/211:38:482
1951799503,8cyclictest0-21swapper/209:19:312
1951799503,43cyclictest0-21swapper/210:00:402
19517995012,32cyclictest0-21swapper/211:31:542
19517995012,32cyclictest0-21swapper/210:32:302
19517995012,32cyclictest0-21swapper/210:32:302
1951099504,9cyclictest0-21swapper/109:50:201
1951099504,9cyclictest0-21swapper/109:50:201
1951099504,40cyclictest0-21swapper/110:56:091
1951099504,40cyclictest0-21swapper/108:57:301
1951099504,40cyclictest0-21swapper/108:57:301
1950699509,35cyclictest0-21swapper/009:32:040
1950699505,13cyclictest0-21swapper/010:58:230
1950699504,41cyclictest0-21swapper/011:29:280
1950699504,41cyclictest0-21swapper/009:36:160
1950699503,41cyclictest0-21swapper/009:02:430
1951799495,38cyclictest0-21swapper/210:53:032
1951799495,38cyclictest0-21swapper/209:11:542
1951799494,40cyclictest0-21swapper/211:25:062
1951799494,40cyclictest0-21swapper/211:25:062
1951799494,40cyclictest0-21swapper/209:52:002
1951799494,39cyclictest0-21swapper/211:10:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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