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2026-02-28 - 19:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Sat Feb 28, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1601399632,7cyclictest30642-21sshd07:03:390
16024995910,5cyclictest0-21swapper/209:52:292
16013995920,34cyclictest3-21ksoftirqd/010:58:080
16013995920,34cyclictest3-21ksoftirqd/010:58:080
1602499575,46cyclictest0-21swapper/211:15:072
1553825710,17sleep20-21swapper/206:25:232
1602499565,45cyclictest0-21swapper/211:41:382
1602499565,45cyclictest0-21swapper/211:41:382
1601799565,5cyclictest0-21swapper/110:51:381
1601799564,46cyclictest0-21swapper/111:44:461
1601799564,46cyclictest0-21swapper/111:44:461
1601399564,46cyclictest0-21swapper/010:11:400
1601399564,28cyclictest0-21swapper/009:20:120
1601399564,28cyclictest0-21swapper/009:20:120
1601399563,48cyclictest0-21swapper/009:48:300
1601399563,48cyclictest0-21swapper/007:18:130
1602499554,46cyclictest0-21swapper/210:21:182
1601399544,6cyclictest0-21swapper/011:54:460
1601399543,45cyclictest20647-21latency_hist09:43:110
16013995423,25cyclictest3-21ksoftirqd/008:58:120
1601399541,47cyclictest11-21rcuc/010:52:080
1602499533,44cyclictest0-21swapper/209:37:362
1601399536,38cyclictest0-21swapper/011:13:450
1601399535,40cyclictest0-21swapper/007:43:240
16013995344,5cyclictest3-21ksoftirqd/009:08:110
1601399534,43cyclictest0-21swapper/009:55:320
1601399534,41cyclictest0-21swapper/010:25:290
1601399532,45cyclictest2945-21ssh10:44:080
16013995313,35cyclictest3-21ksoftirqd/008:48:110
16013995311,36cyclictest0-21swapper/011:26:060
1602499524,42cyclictest0-21swapper/210:59:002
1601399526,40cyclictest0-21swapper/011:49:040
1601399526,40cyclictest0-21swapper/008:34:360
1601399526,39cyclictest0-21swapper/009:28:090
1601399524,42cyclictest0-21swapper/007:53:300
1601399524,41cyclictest0-21swapper/011:07:500
1601399524,41cyclictest0-21swapper/008:03:310
1601399523,44cyclictest0-21swapper/009:33:100
1601399522,46cyclictest22091-21latency_hist10:28:100
16013995211,5cyclictest0-21swapper/011:00:480
1603199512,6cyclictest6395-21rm09:23:303
1602499514,41cyclictest0-21swapper/211:57:312
1602499512,6cyclictest5020-21kworker/2:010:49:382
1601799513,43cyclictest0-21swapper/110:18:331
1601799512,6cyclictest30089-21ssh09:54:291
1601399516,39cyclictest0-21swapper/010:00:560
1601399516,39cyclictest0-21swapper/009:34:550
1601399516,39cyclictest0-21swapper/009:12:550
1601399516,17cyclictest0-21swapper/008:40:240
1601399514,41cyclictest0-21swapper/010:06:400
1601399514,41cyclictest0-21swapper/010:06:400
1601399513,40cyclictest8313-21ssh11:34:100
16013995112,5cyclictest24253-21crond09:48:100
16013995112,31cyclictest0-21swapper/011:45:350
16013995112,31cyclictest0-21swapper/011:45:350
1602499504,41cyclictest0-21swapper/209:54:412
1602499504,40cyclictest0-21swapper/211:04:592
1602499504,40cyclictest0-21swapper/210:15:582
1602499504,40cyclictest0-21swapper/210:05:582
1602499504,40cyclictest0-21swapper/210:05:582
1602499503,42cyclictest0-21swapper/208:48:202
1601799505,39cyclictest0-21swapper/108:52:161
1601799504,41cyclictest0-21swapper/109:21:301
1601799504,41cyclictest0-21swapper/109:21:301
1601799504,40cyclictest0-21swapper/110:42:481
1601399506,38cyclictest0-21swapper/008:28:170
1601399506,38cyclictest0-21swapper/008:28:170
16013995011,33cyclictest0-21swapper/009:14:130
16013995011,33cyclictest0-21swapper/007:08:280
16013995011,33cyclictest0-21swapper/007:08:280
16013995011,32cyclictest0-21swapper/011:21:140
16013995010,8cyclictest0-21swapper/010:42:330
16013995010,33cyclictest0-21swapper/011:11:220
1603199494,39cyclictest0-21swapper/311:52:083
1603199494,39cyclictest0-21swapper/310:52:323
1603199494,39cyclictest0-21swapper/310:41:453
16031994912,31cyclictest0-21swapper/306:28:273
1602499496,37cyclictest0-21swapper/210:09:292
1602499495,38cyclictest0-21swapper/211:44:182
1602499495,38cyclictest0-21swapper/211:44:182
1602499494,39cyclictest0-21swapper/211:29:342
1602499494,39cyclictest0-21swapper/210:36:402
1602499494,39cyclictest0-21swapper/209:20:282
1602499494,39cyclictest0-21swapper/209:20:282
1602499494,39cyclictest0-21swapper/209:17:522
1602499494,39cyclictest0-21swapper/209:00:222
1602499494,19cyclictest0-21swapper/209:27:562
1602499494,19cyclictest0-21swapper/208:30:242
1602499494,19cyclictest0-21swapper/208:30:242
1602499493,42cyclictest0-21swapper/211:26:292
1602499493,41cyclictest0-21swapper/210:53:582
1602499493,41cyclictest0-21swapper/210:53:582
1602499491,43cyclictest30984-21ssh11:22:372
1601799494,39cyclictest0-21swapper/111:38:551
1601799494,39cyclictest0-21swapper/111:38:551
1601799494,39cyclictest0-21swapper/111:34:071
1601799494,39cyclictest0-21swapper/111:32:461
1601799494,39cyclictest0-21swapper/110:34:041
1601799494,20cyclictest0-21swapper/110:09:561
1601799493,42cyclictest0-21swapper/110:47:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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