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2026-01-23 - 08:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa >
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Fri Jan 23, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
750799604,50cyclictest0-21swapper/223:32:502
750799574,46cyclictest0-21swapper/221:05:262
750799564,46cyclictest0-21swapper/221:47:262
750799564,45cyclictest0-21swapper/221:51:352
7500995616,34cyclictest26665-21sendmail_mailst21:38:131
750799557,42cyclictest0-21swapper/222:56:542
750099558,40cyclictest0-21swapper/121:32:071
750099554,45cyclictest0-21swapper/100:09:191
751199544,45cyclictest0-21swapper/323:28:473
750799543,46cyclictest5223-21ssh22:37:442
750799543,24cyclictest0-21swapper/223:32:442
750099545,7cyclictest0-21swapper/121:55:251
750099543,45cyclictest0-21swapper/121:27:351
749699544,45cyclictest0-21swapper/023:44:110
749699544,45cyclictest0-21swapper/023:44:110
750799534,43cyclictest0-21swapper/221:09:262
750799533,44cyclictest0-21swapper/221:29:062
750099534,44cyclictest0-21swapper/121:46:251
750099534,42cyclictest0-21swapper/100:02:221
751199523,43cyclictest0-21swapper/323:20:133
751199523,43cyclictest0-21swapper/323:20:133
750799524,42cyclictest0-21swapper/223:42:432
750799523,43cyclictest0-21swapper/223:23:132
750799523,42cyclictest0-21swapper/220:34:262
750099527,40cyclictest0-21swapper/122:00:051
750099524,42cyclictest0-21swapper/123:25:131
750099522,44cyclictest30362sleep121:07:341
7500995213,5cyclictest0-21swapper/123:35:451
749699527,39cyclictest0-21swapper/000:13:180
749699524,41cyclictest0-21swapper/020:48:260
751199514,41cyclictest0-21swapper/322:39:433
750799515,40cyclictest20522-21diskmemload00:15:092
750799515,40cyclictest0-21swapper/218:47:592
7507995141,5cyclictest29-21ksoftirqd/223:47:432
7507995141,5cyclictest29-21ksoftirqd/223:47:432
750799514,43cyclictest0-21swapper/219:08:322
750799514,43cyclictest0-21swapper/219:08:322
750799514,42cyclictest0-21swapper/220:42:572
750799514,41cyclictest0-21swapper/220:07:582
750799513,42cyclictest0-21swapper/221:33:222
750799513,42cyclictest0-21swapper/221:33:222
750799513,16cyclictest0-21swapper/220:27:482
750099514,41cyclictest0-21swapper/123:55:121
750099514,10cyclictest0-21swapper/122:27:541
750099514,10cyclictest0-21swapper/122:27:541
749699518,16cyclictest0-21swapper/023:35:180
749699514,41cyclictest0-21swapper/022:48:090
751199506,38cyclictest0-21swapper/322:36:433
750799509,35cyclictest0-21swapper/223:08:152
750799508,36cyclictest0-21swapper/222:01:132
750799506,39cyclictest0-21swapper/221:23:362
750799505,8cyclictest0-21swapper/222:38:542
750799504,9cyclictest0-21swapper/222:06:552
750799504,40cyclictest0-21swapper/222:28:342
750799504,40cyclictest0-21swapper/222:28:342
750799504,40cyclictest0-21swapper/219:38:002
750799504,40cyclictest0-21swapper/200:09:472
750799504,22cyclictest0-21swapper/219:58:062
750799503,42cyclictest0-21swapper/221:20:042
750799503,41cyclictest0-21swapper/221:53:132
7507995011,33cyclictest0-21swapper/222:11:012
750099504,41cyclictest0-21swapper/122:18:081
750099504,40cyclictest0-21swapper/122:39:041
750099504,20cyclictest0-21swapper/121:37:221
750099504,20cyclictest0-21swapper/121:37:221
750099503,42cyclictest0-21swapper/123:19:531
750099503,42cyclictest0-21swapper/123:19:531
7500995012,32cyclictest0-21swapper/122:24:101
7500995012,32cyclictest0-21swapper/122:24:101
7500995012,32cyclictest0-21swapper/121:11:041
749699504,41cyclictest0-21swapper/022:59:380
749699504,40cyclictest0-21swapper/021:39:440
749699503,41cyclictest0-21swapper/022:33:040
751199495,19cyclictest0-21swapper/323:34:383
751199494,40cyclictest0-21swapper/322:56:543
750799498,35cyclictest0-21swapper/200:01:232
750799495,5cyclictest0-21swapper/220:49:262
750799495,38cyclictest0-21swapper/220:56:382
750799494,39cyclictest0-21swapper/223:06:202
750799494,39cyclictest0-21swapper/222:14:322
750799494,12cyclictest0-21swapper/219:28:132
750799492,5cyclictest3606-21missed_timers23:18:032
750799492,5cyclictest3606-21missed_timers23:18:032
7507994912,31cyclictest2455-21sshd23:17:212
7507994911,5cyclictest0-21swapper/222:47:142
750099495,38cyclictest0-21swapper/120:55:491
750099494,39cyclictest0-21swapper/123:37:561
750099493,40cyclictest0-21swapper/122:10:551
750099493,40cyclictest0-21swapper/121:18:561
7500994912,5cyclictest0-21swapper/100:06:431
7500994910,33cyclictest0-21swapper/123:31:431
7500994910,33cyclictest0-21swapper/122:16:251
749699495,37cyclictest0-21swapper/023:03:130
749699494,39cyclictest0-21swapper/021:23:260
749699493,41cyclictest0-21swapper/023:55:520
749699493,41cyclictest0-21swapper/022:47:140
7496994910,33cyclictest0-21swapper/023:16:440
751199484,6cyclictest0-21swapper/322:02:553
751199484,37cyclictest0-21swapper/322:29:303
751199484,37cyclictest0-21swapper/322:29:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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