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2026-03-09 - 07:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Mon Mar 09, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
86102860,7sleep20-21swapper/221:58:222
2195099574,46cyclictest0-21swapper/220:58:462
2136225711,17sleep20-21swapper/218:19:342
2195699564,46cyclictest0-21swapper/321:56:353
2195099563,48cyclictest0-21swapper/223:03:352
2195099554,45cyclictest0-21swapper/223:33:332
2195099554,45cyclictest0-21swapper/221:22:102
21950995514,36cyclictest29-21ksoftirqd/222:23:342
21950995514,36cyclictest29-21ksoftirqd/222:23:342
21956995445,5cyclictest37-21ksoftirqd/323:18:343
2195099544,6cyclictest0-21swapper/223:10:332
2195099543,45cyclictest0-21swapper/222:17:562
2195099543,44cyclictest19301-21ssh22:11:552
2195099533,45cyclictest0-21swapper/221:03:462
2194199534,43cyclictest0-21swapper/121:40:511
2167025310,16sleep30-21swapper/318:23:173
2195699525,41cyclictest0-21swapper/321:14:103
2195699524,42cyclictest0-21swapper/321:28:263
2195699524,42cyclictest0-21swapper/321:05:463
2195099526,40cyclictest0-21swapper/223:27:172
2195099526,40cyclictest0-21swapper/222:26:562
2194199524,43cyclictest0-21swapper/122:20:541
2194199524,43cyclictest0-21swapper/122:20:541
2194199524,10cyclictest0-21swapper/121:23:461
2194199522,19cyclictest17947-21ssh23:34:261
2194199522,19cyclictest17947-21ssh23:34:261
21941995218,29cyclictest11469-21sed20:34:071
2195699515,6cyclictest0-21swapper/322:44:443
2195099514,7cyclictest0-21swapper/220:41:572
2195099514,41cyclictest0-21swapper/223:14:232
2195099514,41cyclictest0-21swapper/222:03:252
2195099514,40cyclictest0-21swapper/221:37:412
21950995112,32cyclictest0-21swapper/219:44:022
21950995111,32cyclictest0-21swapper/219:38:592
2194199515,40cyclictest0-21swapper/122:38:471
2194199514,42cyclictest0-21swapper/120:43:441
2194199514,42cyclictest0-21swapper/120:43:441
21936995142,5cyclictest3-21ksoftirqd/020:33:380
2195699505,7cyclictest0-21swapper/320:37:173
2195699505,39cyclictest0-21swapper/323:50:013
21956995013,6cyclictest0-21swapper/320:38:473
2195099506,38cyclictest0-21swapper/220:54:452
2195099503,6cyclictest0-21swapper/221:40:182
2195099503,41cyclictest21868-21kworker/2:122:39:342
2195099502,5cyclictest2458-21diskmemload22:34:202
21950995011,32cyclictest0-21swapper/221:30:492
21950995011,32cyclictest0-21swapper/221:30:492
2194199503,43cyclictest0-21swapper/122:48:041
2194199503,42cyclictest0-21swapper/122:03:351
2195699494,40cyclictest0-21swapper/323:37:033
2195699494,40cyclictest0-21swapper/323:37:033
2195699494,39cyclictest0-21swapper/323:08:593
2195699494,39cyclictest0-21swapper/319:19:013
2195699494,39cyclictest0-21swapper/319:19:013
2195699493,41cyclictest0-21swapper/323:43:533
21956994916,29cyclictest10135-21unixbench_singl23:24:053
21956994912,5cyclictest0-21swapper/323:42:063
21956994912,5cyclictest0-21swapper/322:34:473
21956994912,31cyclictest0-21swapper/321:48:553
2195099496,37cyclictest0-21swapper/222:49:242
2195099496,37cyclictest0-21swapper/221:26:402
2195099496,37cyclictest0-21swapper/220:32:482
2195099496,36cyclictest0-21swapper/220:48:432
2195099495,11cyclictest0-21swapper/219:58:552
2195099494,40cyclictest0-21swapper/222:54:142
2195099494,39cyclictest0-21swapper/223:40:282
2195099494,39cyclictest0-21swapper/222:44:052
2195099494,39cyclictest0-21swapper/222:29:382
2195099494,39cyclictest0-21swapper/218:28:562
2195099493,41cyclictest0-21swapper/220:24:432
21950994910,33cyclictest0-21swapper/223:23:082
2194199494,39cyclictest0-21swapper/123:47:061
2194199494,39cyclictest0-21swapper/122:34:341
2194199494,39cyclictest0-21swapper/121:00:231
2194199494,20cyclictest0-21swapper/121:44:461
2194199493,41cyclictest0-21swapper/122:16:541
21941994911,32cyclictest0-21swapper/122:29:501
2193699493,41cyclictest0-21swapper/020:44:070
2193699493,41cyclictest0-21swapper/020:44:070
213752499,14sleep00-21swapper/018:19:450
2195699488,35cyclictest0-21swapper/321:43:313
2195699488,34cyclictest0-21swapper/323:01:433
2195699488,34cyclictest0-21swapper/322:02:583
2195699484,38cyclictest0-21swapper/323:29:193
2195699484,38cyclictest0-21swapper/322:57:503
2195699484,38cyclictest0-21swapper/322:30:093
2195699484,38cyclictest0-21swapper/322:09:083
2195699484,38cyclictest0-21swapper/321:08:383
2195699484,38cyclictest0-21swapper/320:29:343
2195699482,40cyclictest21048-21ssh21:31:053
2195699482,40cyclictest21048-21ssh21:31:053
2195099488,34cyclictest0-21swapper/221:43:422
2195099486,36cyclictest0-21swapper/223:47:342
2195099486,36cyclictest0-21swapper/223:35:522
2195099486,36cyclictest0-21swapper/223:35:522
2195099484,39cyclictest548-21NetworkManager19:33:392
2195099484,38cyclictest0-21swapper/221:08:552
2195099484,38cyclictest0-21swapper/220:35:272
2195099484,38cyclictest0-21swapper/219:23:552
2195099484,38cyclictest0-21swapper/219:23:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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