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2026-02-16 - 00:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Sun Feb 15, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
333199585,47cyclictest0-21swapper/211:36:562
333199584,47cyclictest0-21swapper/208:45:492
332299575,10cyclictest0-21swapper/109:50:451
332299574,47cyclictest0-21swapper/108:35:561
292225711,17sleep20-21swapper/206:33:222
333199565,45cyclictest0-21swapper/207:35:242
333199554,45cyclictest0-21swapper/211:07:162
332299558,41cyclictest0-21swapper/109:29:181
332299554,46cyclictest0-21swapper/110:17:211
332299554,45cyclictest0-21swapper/109:55:401
332299554,45cyclictest0-21swapper/109:07:311
332299553,47cyclictest0-21swapper/111:08:261
292525510,15sleep00-21swapper/006:33:240
278525510,16sleep30-21swapper/306:31:383
333199546,42cyclictest0-21swapper/210:53:172
333199545,43cyclictest0-21swapper/207:45:432
3331995416,32cyclictest13457-21sshd07:00:252
332299544,44cyclictest0-21swapper/111:30:461
333199534,43cyclictest0-21swapper/211:44:352
333199534,43cyclictest0-21swapper/210:07:282
333199533,45cyclictest0-21swapper/209:19:392
332299533,45cyclictest0-21swapper/109:35:081
332299533,44cyclictest0-21swapper/108:53:511
332299533,44cyclictest0-21swapper/108:53:511
332299533,15cyclictest0-21swapper/107:25:131
332299532,45cyclictest16806-21ssh11:28:451
332299532,27cyclictest22536-21ssh10:10:141
333999523,44cyclictest0-21swapper/311:40:363
333199525,41cyclictest0-21swapper/209:00:492
333199524,42cyclictest0-21swapper/211:27:532
3331995210,36cyclictest0-21swapper/211:56:312
332299525,41cyclictest0-21swapper/109:10:291
332299523,44cyclictest0-21swapper/111:56:431
332299523,24cyclictest0-21swapper/109:38:191
333199513,43cyclictest0-21swapper/211:00:532
333199513,43cyclictest0-21swapper/209:59:092
333199513,43cyclictest0-21swapper/209:44:082
333199513,43cyclictest0-21swapper/209:44:082
3331995111,7cyclictest6754-21switchtime06:40:412
332299519,35cyclictest0-21swapper/110:08:151
332299516,39cyclictest0-21swapper/111:47:591
332299516,39cyclictest0-21swapper/110:03:201
332299516,39cyclictest0-21swapper/108:44:331
332299514,42cyclictest0-21swapper/110:32:271
332299514,41cyclictest0-21swapper/110:26:231
332299514,41cyclictest0-21swapper/110:26:231
332299513,44cyclictest0-21swapper/109:40:191
332299513,44cyclictest0-21swapper/109:40:191
333199506,6cyclictest0-21swapper/210:34:572
333199505,39cyclictest0-21swapper/210:40:342
333199505,39cyclictest0-21swapper/208:37:452
333199504,42cyclictest0-21swapper/209:37:582
333199504,40cyclictest0-21swapper/210:35:512
333199504,40cyclictest0-21swapper/206:53:572
333199503,40cyclictest0-21swapper/210:04:282
333199502,4cyclictest25800-21ls09:30:282
3331995012,5cyclictest0-21swapper/209:23:322
3331995012,32cyclictest0-21swapper/211:48:492
3331995012,32cyclictest0-21swapper/210:12:352
332299507,38cyclictest0-21swapper/108:57:541
332299506,39cyclictest0-21swapper/109:02:531
332299506,38cyclictest0-21swapper/111:19:011
332299506,38cyclictest0-21swapper/110:37:451
332299505,39cyclictest0-21swapper/112:00:471
332299504,40cyclictest0-21swapper/111:04:201
332299504,40cyclictest0-21swapper/109:49:451
3322995011,5cyclictest0-21swapper/108:48:541
3322995010,34cyclictest7453-21latency_hist06:45:131
333999497,37cyclictest0-21swapper/309:47:303
333999495,38cyclictest0-21swapper/309:25:373
333199499,7cyclictest24562-21/usr/sbin/munin07:30:372
333199498,6cyclictest578-21gdbus08:05:112
333199498,35cyclictest0-21swapper/210:24:572
333199496,37cyclictest27-21rcuc/207:20:292
333199495,38cyclictest0-21swapper/206:45:342
333199494,39cyclictest0-21swapper/211:51:282
333199494,39cyclictest0-21swapper/210:55:102
333199493,41cyclictest23377-21ssh08:44:092
333199493,41cyclictest0-21swapper/210:29:572
333199493,41cyclictest0-21swapper/210:29:572
333199493,40cyclictest0-21swapper/208:25:342
333199493,23cyclictest0-21swapper/211:30:532
333199492,7cyclictest28345-21ssh08:50:292
333199492,7cyclictest28345-21ssh08:50:292
333199492,41cyclictest26230-21kworker/2:009:10:292
3331994911,32cyclictest0-21swapper/209:28:442
332299498,35cyclictest0-21swapper/110:24:011
332299495,38cyclictest0-21swapper/111:35:191
332299494,40cyclictest0-21swapper/111:51:051
332299494,39cyclictest0-21swapper/111:41:211
332299494,39cyclictest0-21swapper/110:40:231
332299493,22cyclictest0-21swapper/109:16:291
3322994911,32cyclictest0-21swapper/111:13:371
333199484,39cyclictest0-21swapper/209:07:252
333199484,39cyclictest0-21swapper/207:55:432
333199484,38cyclictest0-21swapper/209:52:122
333199484,38cyclictest0-21swapper/209:48:142
333199484,38cyclictest0-21swapper/208:55:492
333199484,17cyclictest0-21swapper/211:21:492
333199484,17cyclictest0-21swapper/210:15:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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