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2026-01-20 - 09:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Tue Jan 20, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2267699653,56cyclictest0-21swapper/321:09:243
2267699574,47cyclictest0-21swapper/321:22:523
2267699573,27cyclictest8112-21sshd23:47:533
22676995641,10cyclictest0-21swapper/322:39:213
2267699564,46cyclictest0-21swapper/323:33:193
2267699564,46cyclictest0-21swapper/323:33:193
2267699564,46cyclictest0-21swapper/322:48:543
2265699564,7cyclictest0-21swapper/000:04:190
2219525612,38sleep30-21swapper/318:46:463
2267699553,46cyclictest0-21swapper/323:09:503
2267699552,47cyclictest31160-21ssh00:18:383
2265699554,44cyclictest0-21swapper/022:29:010
2267699546,41cyclictest0-21swapper/321:24:493
2267699543,46cyclictest0-21swapper/319:03:523
22676995417,31cyclictest31742-21sshd22:09:493
22676995417,31cyclictest31742-21sshd22:09:493
2265699545,43cyclictest0-21swapper/023:25:500
2265699544,44cyclictest0-21swapper/023:19:500
2265699543,45cyclictest0-21swapper/021:24:170
22656995414,7cyclictest8367-21cat19:34:440
22656995412,36cyclictest22764-21/usr/sbin/munin20:14:510
2231125410,16sleep00-21swapper/018:48:080
2267699536,41cyclictest0-21swapper/323:57:113
2267699534,6cyclictest0-21swapper/321:38:243
2265699534,43cyclictest0-21swapper/022:48:300
2265699532,45cyclictest31211-21ssh21:25:120
2267699524,42cyclictest0-21swapper/321:29:273
2267699524,42cyclictest0-21swapper/300:07:373
2267699523,5cyclictest0-21swapper/323:59:393
2267699523,42cyclictest0-21swapper/322:15:093
2265699525,9cyclictest0-21swapper/023:18:500
2265699525,41cyclictest0-21swapper/022:43:410
2265699524,43cyclictest0-21swapper/020:47:510
2265699524,42cyclictest0-21swapper/021:48:480
2265699524,42cyclictest0-21swapper/021:40:080
2267699516,39cyclictest0-21swapper/323:53:103
2267699515,38cyclictest0-21swapper/323:19:363
22676995113,33cyclictest27714-21latency_hist00:14:203
2267699511,44cyclictest37-21ksoftirqd/321:58:213
2265699515,40cyclictest0-21swapper/023:39:460
2265699514,41cyclictest0-21swapper/022:58:290
2265699514,41cyclictest0-21swapper/022:58:290
2265699514,41cyclictest0-21swapper/021:31:380
2265699513,43cyclictest0-21swapper/022:32:410
22656995112,34cyclictest8773-21unixbench_singl23:04:520
22660995041,5cyclictest21-21ksoftirqd/121:09:231
2265699504,7cyclictest0-21swapper/000:13:290
2265699504,6cyclictest0-21swapper/022:07:110
2265699504,40cyclictest0-21swapper/023:01:290
2265699504,40cyclictest0-21swapper/023:01:290
2265699504,40cyclictest0-21swapper/022:02:270
2265699504,40cyclictest0-21swapper/020:56:290
2265699504,20cyclictest0-21swapper/023:50:410
2265699503,42cyclictest0-21swapper/022:38:410
2265699503,42cyclictest0-21swapper/022:16:410
22656995013,31cyclictest0-21swapper/023:12:510
22656995012,6cyclictest0-21swapper/021:16:550
2267699496,38cyclictest0-21swapper/322:56:513
2267699496,38cyclictest0-21swapper/322:56:513
2267699496,37cyclictest0-21swapper/321:46:373
2267699495,37cyclictest0-21swapper/320:54:383
2267699494,40cyclictest0-21swapper/321:52:173
22676994911,5cyclictest0-21swapper/322:19:263
2265699499,34cyclictest0-21swapper/022:50:420
2265699494,9cyclictest0-21swapper/021:13:030
2265699494,9cyclictest0-21swapper/000:09:090
2265699494,40cyclictest0-21swapper/021:04:060
2265699494,39cyclictest0-21swapper/022:20:180
2265699494,39cyclictest0-21swapper/021:05:320
2265699494,39cyclictest0-21swapper/000:15:200
22656994911,6cyclictest0-21swapper/021:49:290
2267699486,37cyclictest0-21swapper/323:43:183
2267699486,37cyclictest0-21swapper/321:13:073
2267699485,38cyclictest0-21swapper/321:40:423
2267699484,39cyclictest0-21swapper/323:18:003
2267699484,11cyclictest0-21swapper/322:05:083
2267699483,39cyclictest0-21swapper/323:02:003
2267699483,39cyclictest0-21swapper/323:02:003
22676994812,5cyclictest0-21swapper/323:04:333
22676994810,31cyclictest0-21swapper/320:50:173
2265699486,17cyclictest0-21swapper/023:48:400
2265699485,37cyclictest0-21swapper/021:55:270
2265699484,40cyclictest0-21swapper/020:51:240
2265699484,39cyclictest0-21swapper/019:59:360
2265699484,38cyclictest0-21swapper/022:10:530
2265699484,38cyclictest0-21swapper/022:10:530
2265699484,38cyclictest0-21swapper/021:36:380
2265699484,38cyclictest0-21swapper/020:19:530
2265699484,18cyclictest0-21swapper/023:37:230
2267699476,36cyclictest0-21swapper/322:30:483
2267699476,36cyclictest0-21swapper/321:16:293
2267699474,38cyclictest0-21swapper/322:00:273
2267699474,37cyclictest0-21swapper/320:34:383
2267699474,36cyclictest0-21swapper/323:25:383
2267699474,10cyclictest0-21swapper/319:33:523
2267699473,9cyclictest0-21swapper/322:50:003
2267699473,39cyclictest0-21swapper/319:39:253
22676994712,30cyclictest13116-21sed22:29:223
22676994712,30cyclictest0-21swapper/323:37:163
22676994710,5cyclictest0-21swapper/321:00:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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