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2026-02-12 - 09:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Thu Feb 12, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3170222625sleep30-21swapper20:59:593
238122625sleep30-21swapper20:05:333
1236022423sleep40-21swapper22:25:234
2084322323sleep40-21swapper20:37:274
2045422323sleep30-21swapper22:41:393
943822221sleep30-21swapper23:21:403
2645622221sleep20-21swapper20:51:182
1742022221sleep40-21swapper23:36:224
1544122221sleep20-21swapper21:31:192
1333922115sleep40-21swapper19:24:534
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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