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2026-02-22 - 10:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Sun Feb 22, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1100822727sleep40-21swapper22:57:014
1092522725sleep50-21swapper22:55:505
3017122625sleep50-21swapper22:34:055
2006622625sleep40-21swapper20:12:154
540722423sleep50-21swapper23:48:005
2742522423sleep40-21swapper23:29:584
1183722323sleep40-21swapper20:58:574
98522221sleep60-21swapper20:37:466
98522221sleep60-21swapper20:37:466
905022221sleep20-21swapper20:52:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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