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2026-03-01 - 12:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Sat Feb 28, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
463722923sleep50-21swapper08:27:475
2773222928sleep50-21swapper12:14:275
712522827sleep50-21swapper09:35:095
918022726sleep50-21swapper10:36:235
888622726sleep50-21swapper11:36:585
2216422726sleep50-21swapper12:01:065
1831522727sleep40-21swapper07:52:334
654522625sleep40-21swapper10:31:504
513422625sleep20-21swapper07:29:582
508222625sleep40-21swapper07:29:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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