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2026-02-09 - 05:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Mon Feb 09, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39723029sleep20-21swapper21:11:262
882222828sleep30-21swapper20:26:053
2535122625sleep30-21swapper19:58:283
2419722625sleep30-21swapper22:56:503
1999822625sleep30-21swapper19:48:203
1710922625sleep20-21swapper19:40:112
1579422625sleep30-21swapper23:41:083
1108822625sleep30-21swapper21:30:153
1105722625sleep20-21swapper21:29:502
624822525sleep40-21swapper20:22:224
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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