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2026-01-29 - 03:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Thu Jan 29, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2808322625sleep20-21swapper23:33:032
1279622625sleep40-21swapper21:03:404
1016222625sleep20-21swapper20:59:062
89622525sleep30-21swapper23:42:083
2285422525sleep40-21swapper23:24:334
2085822525sleep20-21swapper21:19:222
2974322423sleep20-21swapper21:36:432
201122423sleep30-21swapper20:42:183
1873322424sleep50-21swapper19:12:335
1864222424sleep30-21swapper20:16:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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