You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-02 - 05:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Mon Feb 02, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2991322726sleep50-21swapper22:58:075
227222727sleep40-21swapper00:04:164
941222625sleep40-21swapper19:09:014
789922625sleep50-21swapper20:04:325
3276022625sleep20-21swapper19:53:572
3211122625sleep50-21swapper20:52:345
2938722625sleep50-21swapper23:55:295
272122625sleep60-21swapper19:56:496
2700222625sleep40-21swapper22:49:494
226322625sleep50-21swapper20:55:145
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional