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2026-01-26 - 03:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot5.osadl.org (updated Mon Jan 26, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3148023433sleep10-21swapper23:01:111
2073923433sleep10-21swapper22:39:501
1578423433sleep10-21swapper21:28:521
127623433sleep10-21swapper00:06:091
1067223433sleep10-21swapper21:21:481
565823029sleep20-21swapper20:09:542
527423029sleep20-21swapper21:10:362
3235923029sleep20-21swapper21:01:162
3006323029sleep20-21swapper19:55:222
2889923029sleep20-21swapper22:57:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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