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2026-01-23 - 01:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Thu Jan 22, 2026 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
812022625sleep20-21swapper11:17:062
809222625sleep20-21swapper07:06:012
734622625sleep20-21swapper10:06:552
3232922625sleep20-21swapper12:04:512
2900622625sleep20-21swapper09:46:302
2884022625sleep20-21swapper08:42:122
2496222625sleep20-21swapper10:51:052
2366722625sleep20-21swapper09:36:302
2130422625sleep20-21swapper08:31:082
1618522625sleep20-21swapper11:32:502
1391422625sleep20-21swapper10:28:402
543522521sleep20-21swapper11:11:532
2803322521sleep70-21swapper10:56:147
3217222423sleep20-21swapper06:47:042
3172322421sleep60-21swapper09:52:116
299422421sleep70-21swapper11:10:067
809522323sleep60-21swapper11:16:466
762122322sleep60-21swapper08:04:076
721122323sleep60-21swapper09:03:056
403722323sleep20-21swapper10:01:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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