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2026-03-04 - 07:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Mar 04, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114422727sleep30-21swapper23:24:413
401122625sleep30-21swapper23:31:133
2683122625sleep60-21swapper20:10:536
193022625sleep50-21swapper21:23:585
1762922625sleep20-21swapper22:54:552
711022525sleep40-21swapper22:36:564
748222423sleep50-21swapper21:36:475
438322421sleep50-21swapper22:31:135
1569322423sleep20-21swapper23:53:212
1526622423sleep40-21swapper21:48:464
1034022423sleep40-21swapper20:39:084
973822319sleep40-21swapper22:41:284
3086922323sleep50-21swapper23:18:505
2920622323sleep50-21swapper21:17:105
2680922323sleep50-21swapper20:10:365
2563522323sleep50-21swapper23:10:105
1896622323sleep50-21swapper19:57:395
1375122319sleep50-21swapper18:44:015
1302322323sleep50-21swapper20:44:215
1244222323sleep50-21swapper22:46:575
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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