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2026-02-15 - 17:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Feb 15, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
929623029sleep20-21swapper11:46:192
1210923029sleep30-21swapper11:53:253
543122929sleep30-21swapper07:37:563
436922929sleep40-21swapper10:37:314
2607922927sleep40-21swapper10:17:464
943022823sleep40-21swapper11:48:134
2440422827sleep30-21swapper07:12:113
3179822727sleep30-21swapper09:28:233
2005922727sleep30-21swapper12:07:333
197122727sleep30-21swapper09:31:443
1213222725sleep50-21swapper11:53:435
969422625sleep30-21swapper10:47:143
820422625sleep30-21swapper07:44:283
768222625sleep30-21swapper08:41:583
729022625sleep30-21swapper09:41:203
3221922625sleep30-21swapper08:29:253
3155422625sleep20-21swapper09:24:542
3103622625sleep40-21swapper11:27:094
2974622625sleep30-21swapper07:22:193
2885522625sleep30-21swapper10:24:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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