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2026-01-18 - 07:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Jan 18, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2985423130sleep20-21swapper22:27:202
2492623131sleep20-21swapper20:09:472
99223029sleep20-21swapper20:29:152
44023029sleep70-21swapper20:24:327
2717623029sleep70-21swapper23:24:157
2663523029sleep20-21swapper23:19:292
2528123029sleep20-21swapper19:09:532
785022827sleep70-21swapper23:47:357
2264422825sleep60-21swapper19:05:166
2200022827sleep70-21swapper21:09:307
85922727sleep20-21swapper19:25:212
85922727sleep20-21swapper19:25:212
638622727sleep60-21swapper19:36:386
604022726sleep60-21swapper20:40:086
571322726sleep60-21swapper21:40:266
406422727sleep20-21swapper20:38:362
36122727sleep60-21swapper21:31:466
3263322727sleep70-21swapper22:33:577
3090122727sleep70-21swapper19:23:587
3054522727sleep70-21swapper20:23:527
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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