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2026-02-13 - 18:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Fri Feb 13, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
282622926sleep50-21swapper10:09:005
1890522826sleep50-21swapper10:39:575
1657122625sleep40-21swapper09:34:584
1106922625sleep50-21swapper09:22:425
1075822625sleep40-21swapper10:22:594
2995522519sleep40-21swapper10:00:274
738722423sleep40-21swapper12:17:364
510922423sleep40-21swapper11:13:174
344022423sleep40-21swapper08:08:154
3219222423sleep40-21swapper11:04:054
2508122423sleep40-21swapper07:47:344
883422322sleep40-21swapper08:19:034
609722323sleep60-21swapper08:13:056
473422323sleep50-21swapper12:12:485
328822323sleep50-21swapper09:10:505
3260922323sleep50-21swapper10:05:165
3031522323sleep40-21swapper09:00:494
3003222322sleep50-21swapper08:56:495
2733722322sleep50-21swapper08:51:295
2553022321sleep40-21swapper07:51:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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