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2026-02-01 - 22:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Feb 01, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2495522827sleep30-21swapper10:21:103
2157622521sleep50-21swapper12:15:565
384022423sleep30-21swapper08:39:303
390522321sleep20-21swapper08:40:252
905322221sleep70-21swapper11:54:137
2064922221sleep20-21swapper07:10:542
421422019sleep40-21swapper07:39:534
121522019sleep70-21swapper07:34:287
1190222019sleep40-21swapper08:55:164
1184422019sleep20-21swapper08:54:332
2003621919sleep50-21swapper09:12:055
663321817sleep40-21swapper08:46:194
2558921815sleep30-21swapper08:20:173
2104021817sleep20-21swapper09:14:182
2056621817sleep30-21swapper07:09:433
2008321817sleep20-21swapper09:12:422
1904221817sleep20-21swapper12:12:492
1903521817sleep40-21swapper12:12:424
1053821817sleep60-21swapper11:54:206
278121717sleep50-21swapper11:39:225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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