You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-06 - 22:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Fri Feb 06, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1439422929sleep20-21swapper11:59:202
3064622726sleep50-21swapper11:28:025
2983322726sleep50-21swapper07:27:375
2809622726sleep50-21swapper12:26:365
2795422725sleep50-21swapper11:22:425
237622725sleep40-21swapper08:36:274
890822625sleep40-21swapper11:47:214
3219322625sleep50-21swapper08:33:075
2547222625sleep40-21swapper12:22:114
2453022625sleep50-21swapper07:18:015
2127422625sleep50-21swapper09:14:295
2092922625sleep50-21swapper10:13:035
1924322625sleep40-21swapper08:10:424
1692522625sleep40-21swapper07:05:434
1434822625sleep30-21swapper11:58:413
1390322625sleep50-21swapper08:00:425
1006122625sleep60-21swapper09:51:436
348822521sleep50-21swapper11:36:105
2304222521sleep50-21swapper11:15:455
1643222521sleep50-21swapper07:01:365
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional