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2026-02-21 - 20:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Feb 21, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1420022925sleep30-21swapper10:45:263
552122827sleep40-21swapper11:28:404
1458322726sleep50-21swapper08:44:045
1431322725sleep50-21swapper09:45:025
893822625sleep50-21swapper09:34:375
642622625sleep20-21swapper08:27:042
611222625sleep20-21swapper11:30:312
3271122625sleep40-21swapper10:16:064
3093022625sleep30-21swapper08:14:093
299422625sleep30-21swapper10:20:453
2849422625sleep30-21swapper07:07:423
2445622625sleep30-21swapper11:02:233
2023322625sleep20-21swapper07:53:432
2023322625sleep20-21swapper07:53:432
1984522625sleep30-21swapper08:52:583
1888522625sleep20-21swapper11:53:512
1765022625sleep30-21swapper07:50:003
1389722625sleep40-21swapper10:43:594
1357222625sleep30-21swapper11:44:163
1176122625sleep20-21swapper08:37:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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