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2026-01-20 - 11:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Jan 20, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81822625sleep70-21swapper20:57:247
2738922625sleep70-21swapper23:47:547
1939522625sleep60-21swapper21:29:486
1228222625sleep60-21swapper19:17:276
2022122323sleep60-21swapper19:31:366
393122221sleep20-21swapper20:02:292
3233322221sleep50-21swapper22:53:585
3055422221sleep60-21swapper20:51:386
2838722221sleep40-21swapper18:43:484
2541822221sleep20-21swapper19:39:322
2491922221sleep60-21swapper21:42:206
2152122221sleep60-21swapper23:36:406
1881022221sleep70-21swapper23:31:137
1448422221sleep70-21swapper20:20:507
1374322221sleep60-21swapper22:20:146
3034722121sleep70-21swapper20:48:437
2221122019sleep70-21swapper21:36:457
125622019sleep70-21swapper18:53:197
690621919sleep60-21swapper19:06:556
690621919sleep60-21swapper19:06:556
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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