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2026-01-15 - 05:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Thu Jan 15, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509722727sleep60-21swapper20:05:016
2673222727sleep70-21swapper19:44:137
2527822727sleep60-21swapper23:43:016
3225522625sleep60-21swapper18:52:026
2975922625sleep60-21swapper19:51:246
2969522625sleep60-21swapper18:48:346
2828222625sleep70-21swapper22:47:567
2818722625sleep60-21swapper22:46:356
2544222625sleep40-21swapper21:41:264
240822625sleep60-21swapper19:59:416
2383922625sleep60-21swapper20:40:466
1881722625sleep60-21swapper19:30:366
1831222625sleep60-21swapper20:28:146
1795622625sleep30-21swapper23:31:213
107022625sleep70-21swapper22:56:367
790322423sleep70-21swapper19:07:087
1803722423sleep60-21swapper22:31:146
2613922323sleep70-21swapper21:45:297
1723522323sleep70-21swapper23:27:417
1528222323sleep60-21swapper21:22:566
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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