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2026-02-03 - 18:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Feb 03, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1976022423sleep20-21swapper07:39:102
1478422423sleep40-21swapper08:36:184
599922221sleep20-21swapper10:19:232
3099322221sleep50-21swapper07:02:395
3015322221sleep50-21swapper11:06:245
2309622221sleep30-21swapper08:52:493
1927022221sleep50-21swapper10:43:275
2449322019sleep40-21swapper11:56:414
1744522019sleep40-21swapper08:41:144
597221817sleep50-21swapper10:19:025
3224621817sleep40-21swapper12:08:094
318421817sleep60-21swapper11:17:136
318221817sleep40-21swapper11:17:114
3051521814sleep50-21swapper10:06:385
2475421817sleep50-21swapper10:55:275
2262921817sleep50-21swapper08:49:075
2159621817sleep40-21swapper11:48:324
1708221817sleep40-21swapper09:40:204
1625421817sleep40-21swapper11:38:244
103021817sleep40-21swapper07:04:304
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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