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2026-02-28 - 04:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Feb 28, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2819023130sleep50-21swapper21:54:575
2819023130sleep50-21swapper21:54:575
633323029sleep20-21swapper22:12:382
723922925sleep50-21swapper20:15:415
723922925sleep50-21swapper20:15:415
3078722726sleep50-21swapper21:58:575
1402622725sleep50-21swapper23:28:125
665022625sleep50-21swapper21:12:155
595222626sleep40-21swapper23:12:104
484122625sleep20-21swapper19:09:362
484122625sleep20-21swapper19:09:362
3017922625sleep40-21swapper23:59:564
903822521sleep60-21swapper22:18:106
703722423sleep30-21swapper20:12:513
703722423sleep30-21swapper20:12:513
962022323sleep60-21swapper20:16:386
678022323sleep40-21swapper21:14:064
491922323sleep50-21swapper19:10:435
491922323sleep50-21swapper19:10:435
455722323sleep40-21swapper20:10:284
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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