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2026-02-18 - 17:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Feb 18, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
464122923sleep50-21swapper12:22:015
2494222928sleep50-21swapper08:57:305
774322726sleep50-21swapper10:23:255
749622726sleep50-21swapper11:24:475
2920722726sleep50-21swapper11:05:025
87322625sleep40-21swapper07:11:014
1583422625sleep20-21swapper10:39:382
1551222625sleep50-21swapper11:40:005
1900622521sleep60-21swapper09:46:456
1626522419sleep40-21swapper09:40:504
1122322423sleep40-21swapper08:30:084
1073822423sleep40-21swapper09:28:104
1935822321sleep50-21swapper08:46:495
1888722323sleep20-21swapper09:45:042
1644622323sleep40-21swapper08:38:324
1584722323sleep60-21swapper10:39:506
1314122323sleep40-21swapper10:34:204
805722221sleep20-21swapper09:22:562
742222221sleep60-21swapper11:23:446
595722221sleep50-21swapper08:21:055
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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