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2026-01-19 - 20:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Mon Jan 19, 2026 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1338223231sleep70-21swapper09:42:497
60823130sleep60-21swapper07:17:466
461523131sleep60-21swapper11:26:596
1390623130sleep60-21swapper07:40:356
2653423029sleep60-21swapper10:05:126
2579823029sleep60-21swapper12:04:376
2395623029sleep70-21swapper10:01:297
2367723029sleep70-21swapper11:02:277
2324723029sleep70-21swapper12:01:187
2182523029sleep60-21swapper07:54:206
200523029sleep70-21swapper11:23:007
1811923029sleep60-21swapper10:49:146
1627723029sleep60-21swapper09:48:086
1594323029sleep60-21swapper09:46:166
1240723029sleep60-21swapper11:38:526
784922929sleep70-21swapper09:30:087
745522925sleep50-21swapper10:29:285
2447922929sleep70-21swapper07:59:097
2415122925sleep60-21swapper08:59:186
2107922929sleep70-21swapper09:53:297
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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