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2026-01-31 - 04:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Jan 31, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2595722827sleep30-21swapper22:13:243
2023022827sleep30-21swapper23:02:463
2023022827sleep30-21swapper23:02:463
922622625sleep20-21swapper23:43:102
84122625sleep30-21swapper00:28:413
719622625sleep30-21swapper21:37:143
2528622625sleep20-21swapper00:13:352
1780122625sleep30-21swapper21:56:113
1780122625sleep30-21swapper21:56:113
1752122625sleep20-21swapper22:57:082
1446722625sleep30-21swapper23:51:433
1290922625sleep30-21swapper20:47:453
1258522625sleep20-21swapper21:48:022
3079522423sleep40-21swapper23:21:194
2610422423sleep20-21swapper21:10:332
2528722423sleep30-21swapper00:13:363
251422424sleep50-21swapper19:26:405
183122423sleep30-21swapper21:27:143
103422423sleep40-21swapper23:26:394
986622323sleep30-21swapper21:42:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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