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2026-02-11 - 23:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Feb 11, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1608323231sleep50-21swapper08:46:115
2168223029sleep20-21swapper07:54:542
449722727sleep40-21swapper10:23:024
254922727sleep40-21swapper08:18:254
2148222727sleep50-21swapper08:57:005
2999022625sleep50-21swapper07:09:205
2735722625sleep50-21swapper07:04:485
2696222625sleep20-21swapper08:04:072
2441922625sleep50-21swapper08:00:505
2291922625sleep50-21swapper11:59:145
1770422625sleep70-21swapper09:47:277
497422323sleep60-21swapper09:24:546
279922321sleep70-21swapper08:21:567
2346222321sleep50-21swapper11:02:005
523622221sleep70-21swapper08:23:407
394222221sleep60-21swapper12:25:006
244022221sleep20-21swapper09:21:462
2180022221sleep50-21swapper07:56:345
1555422221sleep70-21swapper09:43:357
1553022221sleep40-21swapper09:43:164
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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