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2026-02-01 - 09:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Jan 31, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1184123231sleep50-21swapper11:15:185
634322725sleep50-21swapper12:07:515
1685222726sleep50-21swapper12:25:365
1261522727sleep40-21swapper09:16:244
3097522625sleep50-21swapper10:51:575
2913222625sleep40-21swapper08:48:474
1312922625sleep50-21swapper08:18:475
467222424sleep40-21swapper09:02:164
2834022423sleep40-21swapper10:47:244
2812822423sleep50-21swapper11:49:195
211322423sleep30-21swapper08:58:553
2054922421sleep50-21swapper09:30:265
2029422423sleep40-21swapper10:31:474
925222323sleep30-21swapper11:11:233
712422323sleep20-21swapper10:09:042
700422323sleep50-21swapper10:07:235
447822323sleep50-21swapper10:04:275
409622323sleep40-21swapper11:03:564
401022322sleep50-21swapper11:02:455
364022321sleep20-21swapper11:00:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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