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2026-02-11 - 10:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Feb 11, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2393322827sleep30-21swapper21:58:073
2222122723sleep50-21swapper19:56:285
65122625sleep30-21swapper19:14:413
45122625sleep40-21swapper20:16:524
41122625sleep30-21swapper20:16:193
3042122625sleep30-21swapper19:09:213
2693622625sleep20-21swapper21:03:002
2456922625sleep40-21swapper21:02:144
2420622625sleep20-21swapper22:01:582
2147322625sleep20-21swapper21:56:052
2147322625sleep20-21swapper21:56:052
1887822625sleep20-21swapper21:52:052
1616622625sleep30-21swapper21:46:383
1588022625sleep20-21swapper22:47:272
1094822625sleep20-21swapper20:33:232
739122523sleep40-21swapper23:30:274
2608022525sleep40-21swapper00:05:244
2340922525sleep30-21swapper00:00:193
462322423sleep30-21swapper23:24:023
462322423sleep30-21swapper23:24:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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