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2026-02-14 - 16:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Feb 14, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1014422925sleep50-21swapper09:06:055
392422726sleep50-21swapper11:58:125
1268622726sleep50-21swapper10:14:165
686022625sleep40-21swapper11:02:094
2112822625sleep40-21swapper08:25:394
1101022625sleep20-21swapper07:08:382
1061522625sleep30-21swapper08:07:533
786022423sleep40-21swapper08:01:384
758522422sleep50-21swapper09:02:375
3153922321sleep50-21swapper09:46:475
3145122321sleep40-21swapper09:45:424
2878022319sleep50-21swapper09:40:395
2712422323sleep50-21swapper07:40:105
2545222323sleep40-21swapper11:36:024
2421822323sleep50-21swapper07:31:465
240422323sleep40-21swapper08:54:524
240422323sleep40-21swapper08:54:524
2395922323sleep50-21swapper08:33:005
2348522321sleep50-21swapper09:31:105
2107922323sleep60-21swapper09:29:516
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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