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2026-02-27 - 03:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Fri Feb 27, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1901222928sleep50-21swapper21:10:115
551222826sleep50-21swapper20:42:585
2244622827sleep50-21swapper19:16:155
1616722827sleep40-21swapper21:02:424
1439922827sleep50-21swapper19:00:395
3258122726sleep50-21swapper19:32:005
2960422727sleep40-21swapper21:29:074
2684422727sleep40-21swapper21:22:514
253522625sleep50-21swapper21:38:285
2114822625sleep50-21swapper22:12:375
1971522625sleep20-21swapper19:10:202
1821822625sleep50-21swapper23:08:475
1579722625sleep50-21swapper22:02:215
1286222625sleep40-21swapper22:58:304
1125222625sleep50-21swapper19:53:445
2229122519sleep40-21swapper19:14:064
188022521sleep30-21swapper23:39:033
2996522423sleep40-21swapper20:29:214
2390722422sleep50-21swapper22:18:545
1542422422sleep50-21swapper23:01:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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