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2026-02-10 - 22:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Feb 10, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
774122827sleep40-21swapper10:30:274
774122827sleep40-21swapper10:30:274
2904322723sleep40-21swapper11:09:484
3167522625sleep20-21swapper11:14:182
2703022625sleep20-21swapper09:04:142
2451922625sleep20-21swapper09:01:262
2391922625sleep30-21swapper08:58:153
1065922521sleep30-21swapper09:34:083
802922423sleep40-21swapper09:29:374
2176222424sleep50-21swapper08:55:125
1839222424sleep50-21swapper10:50:055
834922323sleep70-21swapper08:29:147
2453422323sleep60-21swapper09:01:386
2326822323sleep70-21swapper11:58:257
218522323sleep40-21swapper11:22:134
990722221sleep20-21swapper11:33:152
855022221sleep20-21swapper08:32:052
84822221sleep20-21swapper07:17:462
839022221sleep30-21swapper08:29:503
817022221sleep20-21swapper09:31:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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