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2026-01-27 - 04:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Jan 27, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345123029sleep30-21swapper23:14:563
2549723029sleep20-21swapper21:55:092
1418423029sleep20-21swapper23:35:522
2498122926sleep50-21swapper23:57:325
566322826sleep50-21swapper00:18:135
1745222826sleep50-21swapper21:39:275
1708922827sleep50-21swapper22:39:135
159622827sleep50-21swapper21:12:225
1003022826sleep50-21swapper20:27:485
452022726sleep50-21swapper20:15:165
374222727sleep50-21swapper22:14:085
3108622726sleep50-21swapper21:03:425
2811822725sleep40-21swapper21:59:194
1712422726sleep40-21swapper22:39:444
1144922726sleep50-21swapper23:29:555
670222625sleep20-21swapper21:18:192
573722625sleep40-21swapper00:19:164
325222625sleep40-21swapper00:16:524
3124722623sleep50-21swapper22:08:005
2843422625sleep40-21swapper20:58:534
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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