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2026-03-03 - 06:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Mar 03, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2100922928sleep50-21swapper19:47:285
2100922928sleep50-21swapper19:47:285
364222726sleep50-21swapper22:14:215
2319022726sleep50-21swapper20:51:065
1459122726sleep40-21swapper22:38:214
1162622727sleep40-21swapper22:29:164
749322625sleep40-21swapper22:24:044
350622625sleep40-21swapper23:17:504
3112922625sleep50-21swapper21:05:225
3006022625sleep40-21swapper00:06:164
3006022625sleep40-21swapper00:06:164
2792022625sleep50-21swapper23:03:275
2669522625sleep50-21swapper18:57:105
2664022625sleep50-21swapper19:58:565
1248122625sleep40-21swapper20:30:324
2019022521sleep30-21swapper21:46:423
2727222421sleep50-21swapper23:59:295
185222424sleep50-21swapper20:11:125
1814522423sleep40-21swapper19:39:424
1244322423sleep50-21swapper20:30:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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