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2026-02-19 - 19:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Thu Feb 19, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2754022925sleep30-21swapper09:08:363
915822827sleep40-21swapper07:32:584
675022826sleep50-21swapper07:31:395
1653722827sleep40-21swapper09:48:464
579122726sleep40-21swapper09:27:504
390922727sleep30-21swapper07:24:083
814722625sleep20-21swapper10:33:182
610422625sleep20-21swapper08:27:222
528122625sleep20-21swapper11:30:242
3146822625sleep20-21swapper12:16:582
3105322625sleep30-21swapper07:15:523
3070422625sleep20-21swapper08:15:452
2987022625sleep20-21swapper09:12:032
2675322625sleep60-21swapper11:07:156
266122625sleep50-21swapper11:26:035
266122625sleep50-21swapper11:26:035
2298722625sleep20-21swapper08:01:532
2193122625sleep40-21swapper09:59:354
2031722625sleep20-21swapper06:54:542
2021922625sleep60-21swapper06:53:306
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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