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2026-01-17 - 07:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Jan 17, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
605123029sleep00-21swapper18:44:540
395622625sleep70-21swapper23:42:317
2560222625sleep70-21swapper23:22:077
1378722625sleep60-21swapper18:55:326
98522423sleep60-21swapper22:35:086
3005022323sleep60-21swapper19:29:186
3005022323sleep60-21swapper19:29:186
421922221sleep20-21swapper22:41:282
3129022221sleep20-21swapper22:32:082
2847122221sleep20-21swapper23:29:462
2834122221sleep70-21swapper23:27:597
2818522221sleep20-21swapper23:25:542
1834722221sleep60-21swapper21:07:456
137522221sleep20-21swapper23:39:382
1266422221sleep20-21swapper21:57:432
1071322221sleep20-21swapper19:52:582
2641522117sleep50-21swapper21:23:455
2107522121sleep70-21swapper21:13:387
274222019sleep20-21swapper19:35:222
920021919sleep20-21swapper23:51:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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