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2026-02-21 - 07:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Feb 21, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2951522625sleep30-21swapper23:54:033
850422221sleep20-21swapper22:14:062
3270622221sleep20-21swapper21:56:542
2209322221sleep30-21swapper21:37:503
1231522221sleep30-21swapper19:20:413
1149822221sleep50-21swapper21:18:555
2815222019sleep40-21swapper19:48:114
1350522019sleep40-21swapper23:24:194
1216422019sleep40-21swapper19:18:344
1155422019sleep40-21swapper21:19:424
355721918sleep30-21swapper21:04:453
3082721918sleep30-21swapper19:53:143
3007721917sleep40-21swapper20:51:014
2667821918sleep40-21swapper23:46:444
1702921918sleep40-21swapper20:26:444
1634221918sleep30-21swapper22:26:483
1044121915sleep30-21swapper00:18:283
933321817sleep30-21swapper19:11:133
847521817sleep30-21swapper22:13:433
763921817sleep30-21swapper00:11:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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