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2026-02-02 - 18:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Mon Feb 02, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
929223130sleep50-21swapper08:22:475
1391123029sleep40-21swapper11:34:054
874822826sleep50-21swapper09:19:375
2741422826sleep50-21swapper12:01:195
2286922825sleep50-21swapper07:46:145
1099722826sleep50-21swapper12:30:325
1099722826sleep50-21swapper12:30:325
3005922725sleep50-21swapper09:59:065
2549122723sleep40-21swapper07:50:374
1117822726sleep40-21swapper12:33:034
1117822726sleep40-21swapper12:33:034
1111522727sleep60-21swapper10:25:166
887122625sleep50-21swapper10:23:235
84122625sleep50-21swapper09:07:135
834522625sleep40-21swapper10:18:504
659222625sleep20-21swapper08:17:162
603622625sleep50-21swapper11:20:535
47422625sleep40-21swapper10:07:064
348022625sleep50-21swapper09:10:335
3059022625sleep50-21swapper09:01:445
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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