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2026-01-13 - 16:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Jan 13, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3211223029sleep60-21swapper08:24:096
2358822726sleep20-21swapper11:13:392
2108922727sleep50-21swapper11:11:025
504022625sleep20-21swapper07:31:232
2630122625sleep70-21swapper11:19:207
2384522625sleep60-21swapper10:12:376
231322625sleep20-21swapper10:34:412
2146922625sleep70-21swapper11:12:247
2064822625sleep20-21swapper12:09:412
1641522625sleep20-21swapper07:57:162
1595822625sleep20-21swapper06:49:452
1322922521sleep60-21swapper09:53:086
3161922423sleep20-21swapper11:29:072
1825922423sleep60-21swapper11:03:426
551422322sleep70-21swapper08:37:227
3209822323sleep20-21swapper07:21:472
3174822322sleep60-21swapper11:30:556
3170822323sleep70-21swapper11:30:247
2962322319sleep20-21swapper09:23:432
2913722323sleep20-21swapper11:26:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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