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2026-01-25 - 05:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Jan 25, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93223029sleep10-21swapper00:14:141
758623029sleep10-21swapper20:20:141
715123029sleep10-21swapper21:20:161
636023029sleep10-21swapper23:21:241
612023029sleep10-21swapper00:23:581
3212123029sleep10-21swapper20:07:261
3115023029sleep10-21swapper22:06:021
3040023029sleep10-21swapper00:07:341
2955123029sleep10-21swapper20:03:421
275823029sleep10-21swapper19:11:001
2538823029sleep10-21swapper22:56:041
2349623029sleep10-21swapper20:49:351
2325223029sleep10-21swapper21:52:171
2158723029sleep10-21swapper19:49:011
196423029sleep10-21swapper20:09:341
1957923029sleep10-21swapper23:45:171
1825523029sleep10-21swapper19:39:331
176823029sleep10-21swapper21:09:521
1759323029sleep10-21swapper22:43:391
1705023029sleep10-21swapper23:42:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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