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2026-02-23 - 09:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Mon Feb 23, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2326923130sleep50-21swapper20:07:155
3094122925sleep50-21swapper21:22:305
2303022926sleep50-21swapper21:08:465
1151922726sleep50-21swapper22:46:415
876222625sleep50-21swapper22:40:255
836422625sleep50-21swapper23:39:395
3137822625sleep20-21swapper20:23:452
2083922625sleep50-21swapper19:00:415
1689622625sleep50-21swapper22:57:135
1389822625sleep50-21swapper23:52:195
1111822625sleep40-21swapper23:45:464
105122625sleep50-21swapper21:25:585
971322521sleep40-21swapper20:44:044
52122521sleep50-21swapper23:28:355
1131622523sleep50-21swapper23:48:355
428622423sleep40-21swapper20:32:514
2065522423sleep40-21swapper20:02:584
912522323sleep50-21swapper21:40:395
894222323sleep60-21swapper23:44:286
761622323sleep60-21swapper19:39:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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