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2026-03-05 - 08:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Thu Mar 05, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1521223225sleep40-21swapper22:46:594
2701222726sleep50-21swapper20:07:195
1917322726sleep50-21swapper18:49:165
943822625sleep50-21swapper23:35:585
2617922625sleep40-21swapper22:06:024
2181222525sleep40-21swapper18:53:554
411722423sleep40-21swapper23:26:134
2995222323sleep50-21swapper19:11:005
2957222323sleep40-21swapper20:10:544
258822323sleep40-21swapper20:21:344
998422221sleep20-21swapper21:33:192
998422221sleep20-21swapper21:33:192
971622221sleep20-21swapper22:34:412
776322221sleep70-21swapper20:29:217
672722221sleep50-21swapper23:30:305
546922221sleep20-21swapper19:24:182
483422221sleep40-21swapper21:25:524
3131322221sleep50-21swapper22:13:155
2911322221sleep60-21swapper21:09:386
2836322221sleep20-21swapper23:09:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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