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2026-01-18 - 19:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Jan 18, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
921222323sleep70-21swapper10:29:377
2527422322sleep30-21swapper08:59:063
1533022323sleep50-21swapper08:40:435
1466822323sleep60-21swapper10:41:136
420922221sleep20-21swapper08:17:202
2794922221sleep20-21swapper11:05:262
2261422221sleep20-21swapper10:55:252
1160222221sleep50-21swapper11:35:305
73622019sleep70-21swapper11:14:117
889421919sleep60-21swapper11:30:026
3132221917sleep70-21swapper08:08:287
2066721919sleep40-21swapper07:48:414
1799921917sleep20-21swapper08:45:452
1771321919sleep60-21swapper09:46:396
1695321919sleep50-21swapper11:45:465
1526921917sleep40-21swapper07:37:444
1505021919sleep60-21swapper09:41:436
140621917sleep20-21swapper08:11:192
1281321919sleep60-21swapper08:37:486
927521817sleep20-21swapper07:21:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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