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2026-01-14 - 15:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Jan 14, 2026 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
829323029sleep20-21swapper07:36:202
829323029sleep20-21swapper07:36:202
2118123029sleep20-21swapper10:01:532
14199993029cyclictest0-21swapper06:46:370
493422723sleep70-21swapper10:33:357
1032422726sleep20-21swapper10:44:102
982722625sleep20-21swapper11:42:042
550122625sleep20-21swapper08:31:422
3251722625sleep20-21swapper07:19:232
3165922625sleep20-21swapper11:24:122
3149622625sleep70-21swapper11:21:537
2921322625sleep20-21swapper10:17:212
2442222625sleep70-21swapper07:03:037
2438722625sleep20-21swapper07:02:342
2380322625sleep70-21swapper11:11:127
2379022625sleep20-21swapper09:03:592
2372522625sleep30-21swapper11:10:043
2344222625sleep20-21swapper12:11:012
2111722625sleep20-21swapper11:05:552
1897322625sleep20-21swapper07:56:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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