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2026-02-25 - 00:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Tue Feb 24, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2217622923sleep50-21swapper10:13:375
890222727sleep30-21swapper10:50:483
632222727sleep40-21swapper10:47:054
2273422726sleep40-21swapper10:18:004
2002322726sleep40-21swapper10:12:244
692222625sleep40-21swapper08:46:054
646522621sleep40-21swapper09:44:234
2808022625sleep50-21swapper11:28:275
2362622625sleep40-21swapper07:16:094
2114522625sleep20-21swapper12:13:302
1842722625sleep50-21swapper07:08:025
1807122625sleep40-21swapper08:07:554
1196022625sleep40-21swapper10:58:254
1196022625sleep40-21swapper10:58:254
911522521sleep40-21swapper09:49:034
690022521sleep30-21swapper08:45:483
665522522sleep50-21swapper09:47:045
961922423sleep40-21swapper09:53:194
2794722421sleep50-21swapper10:26:175
1766722424sleep60-21swapper09:07:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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