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2026-02-25 - 19:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Feb 25, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1986922521sleep40-21swapper11:18:384
2407522423sleep20-21swapper08:27:502
1581222323sleep40-21swapper08:11:594
1147722323sleep60-21swapper12:02:576
84822221sleep50-21swapper11:44:565
2953222221sleep50-21swapper07:37:355
210122221sleep40-21swapper08:46:484
2037222221sleep40-21swapper10:20:524
2037222221sleep40-21swapper10:20:524
1810722019sleep40-21swapper09:16:414
1810722019sleep40-21swapper09:16:414
499021919sleep40-21swapper07:49:504
3160621917sleep50-21swapper08:38:575
3093421919sleep70-21swapper09:37:577
2586121917sleep50-21swapper09:28:115
2043221917sleep70-21swapper10:21:437
2043221917sleep70-21swapper10:21:437
1204521917sleep50-21swapper11:06:145
951021817sleep20-21swapper09:58:092
763121817sleep60-21swapper06:53:026
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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