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2026-02-25 - 12:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Feb 25, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2214823029sleep20-21swapper18:54:442
964122625sleep30-21swapper23:33:193
836322625sleep20-21swapper19:28:302
757122626sleep40-21swapper22:31:584
710322625sleep20-21swapper23:30:142
3161722625sleep20-21swapper23:17:262
3127622625sleep20-21swapper00:17:202
2655222625sleep20-21swapper22:06:192
2056322625sleep20-21swapper23:56:392
1590322625sleep20-21swapper21:46:342
1532022625sleep20-21swapper22:43:162
1284622625sleep20-21swapper22:41:002
827722525sleep40-21swapper20:32:104
355422523sleep50-21swapper19:23:045
34822521sleep50-21swapper19:14:485
2455422521sleep50-21swapper20:00:585
1285922525sleep40-21swapper23:43:054
3255622423sleep40-21swapper20:16:014
2987722423sleep40-21swapper20:10:494
1817322423sleep60-21swapper22:50:496
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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