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2026-01-14 - 06:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Wed Jan 14, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3071823131sleep60-21swapper00:15:256
1842123131sleep70-21swapper19:47:167
1606022825sleep60-21swapper20:47:026
1606022825sleep60-21swapper20:47:026
973122723sleep60-21swapper22:35:456
935922723sleep60-21swapper23:35:166
698022727sleep60-21swapper22:29:376
2559922727sleep20-21swapper22:02:122
2440722727sleep60-21swapper18:59:546
2166022727sleep60-21swapper18:53:466
2080622726sleep60-21swapper21:56:246
202622726sleep60-21swapper21:20:156
200622723sleep70-21swapper22:22:027
1863622727sleep60-21swapper19:48:366
1509622727sleep60-21swapper23:47:006
110022726sleep60-21swapper23:18:036
962522625sleep20-21swapper22:34:132
809622625sleep60-21swapper19:30:356
786422625sleep20-21swapper19:27:192
778322625sleep40-21swapper20:31:074
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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