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2026-01-24 - 15:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sat Jan 24, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
769722221sleep20-21swapper08:33:032
59222221sleep20-21swapper12:23:512
27428992217cyclictest0-21swapper08:19:460
27428992016cyclictest0-21swapper08:05:260
27428992013cyclictest0-21swapper10:09:480
27428991913cyclictest0-21swapper12:12:150
27428991913cyclictest0-21swapper11:33:250
27428991913cyclictest0-21swapper09:07:280
27428991913cyclictest0-21swapper07:19:010
370921817sleep30-21swapper11:27:423
3127821817sleep10-21swapper10:18:581
2886721817sleep30-21swapper10:14:353
27428991818cyclictest0-21swapper10:58:240
27428991813cyclictest0-21swapper12:35:150
27428991813cyclictest0-21swapper12:24:400
27428991813cyclictest0-21swapper07:50:260
27428991813cyclictest0-21swapper07:24:540
27428991811cyclictest0-21swapper11:04:430
27428991811cyclictest0-21swapper08:45:040
27428991811cyclictest0-21swapper07:44:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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