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2026-02-22 - 20:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5.osadl.org (updated Sun Feb 22, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1683723030sleep40-21swapper11:56:294
3077122827sleep40-21swapper10:20:264
443222625sleep50-21swapper08:30:315
359822625sleep20-21swapper11:33:062
2552822625sleep50-21swapper10:11:465
2552822625sleep50-21swapper10:11:465
2111622625sleep30-21swapper07:00:093
180622625sleep20-21swapper08:26:352
1557022625sleep20-21swapper07:52:022
1484622625sleep20-21swapper09:51:342
881322525sleep30-21swapper11:41:153
798722525sleep40-21swapper07:39:564
1955722525sleep30-21swapper12:02:123
1329322524sleep50-21swapper07:49:495
1161622525sleep30-21swapper11:48:123
556322423sleep20-21swapper07:34:582
339322423sleep40-21swapper11:30:124
3063222423sleep20-21swapper09:19:572
2839122423sleep40-21swapper10:19:294
2802122423sleep40-21swapper11:19:004
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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