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2026-08-11 - 19:03

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Phytec
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot5s.osadl.org (updated Tue Aug 11, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87971995748,5cyclictest154280-21latency_hist10:20:013
87960995524,5cyclictest156073-21idleruntime-cro10:25:011
87960995445,5cyclictest119603-21idleruntime-cro08:39:591
87960995219,8cyclictest169476-21grep11:00:261
87956995040,6cyclictest112154-21unixbench_singl08:15:260
87960994919,5cyclictest0-21swapper/107:10:261
87960994836,8cyclictest181871-21sendmail11:40:001
87956994633,9cyclictest121ktimers/011:00:130
87956994633,5cyclictest147090-21kworker/u8:1+events_unbound10:09:030
87956994532,9cyclictest176273-21grep11:20:240
87960994231,8cyclictest231ktimers/109:45:141
87960994228,11cyclictest231ktimers/112:00:141
87960994228,11cyclictest231ktimers/112:00:141
87965994133,6cyclictest311ktimers/208:05:142
8796599410,9cyclictest0-21swapper/208:00:122
87960994133,4cyclictest0-21swapper/108:20:011
87956994135,4cyclictest162962-21kworker/u8:1+events_unbound10:49:120
87956994135,4cyclictest148863-21kworker/u8:2+events_unbound10:19:080
87956994130,7cyclictest140094-21basename09:40:010
87956994130,5cyclictest131rcu_preempt07:20:240
87971994032,4cyclictest0-21swapper/311:25:013
87956994032,5cyclictest136670-21latency_hist09:30:010
87960993927,9cyclictest231ktimers/111:15:141
87956993932,5cyclictest112250-21kworker/u8:0+events_unbound08:38:410
87956993922,5cyclictest131rcu_preempt07:36:130
87965993832,4cyclictest126051-21kworker/u8:2+events_unbound08:58:442
87965993831,4cyclictest163107-21munin-run10:45:002
87965993831,4cyclictest147305-21cron10:00:002
87965993831,4cyclictest147305-21cron09:59:592
87965993826,7cyclictest0-21swapper/211:10:262
87965993825,9cyclictest148591-21grep10:00:282
87960993830,4cyclictest0-21swapper/110:40:001
87960993830,4cyclictest0-21swapper/110:40:001
87960993827,7cyclictest0-21swapper/108:30:251
87956993831,5cyclictest95201-21kworker/u8:0+events_unbound07:28:340
87956993828,5cyclictest0-21swapper/010:24:070
87956993825,5cyclictest110501-21kworker/u8:1-events_freezable_power_08:11:570
87956993813,18cyclictest131rcu_preempt10:00:170
87965993726,6cyclictest0-21swapper/210:05:142
87960993729,4cyclictest0-21swapper/110:20:011
87956993718,12cyclictest11-21ksoftirqd/011:15:150
87956993718,10cyclictest131rcu_preempt08:24:260
87956993716,10cyclictest131rcu_preempt07:50:120
87956993716,10cyclictest131rcu_preempt07:50:120
87971993625,7cyclictest178867-21cut11:30:163
87965993629,4cyclictest95517-21idleruntime-cro07:30:012
87965993629,4cyclictest138366-21auditctl09:35:012
87965993628,4cyclictest0-21swapper/210:50:172
8795699367,13cyclictest11-21ksoftirqd/012:01:350
8795699367,13cyclictest11-21ksoftirqd/012:01:350
87956993625,4cyclictest131rcu_preempt08:00:210
87956993624,4cyclictest131rcu_preempt12:17:020
87956993624,4cyclictest131rcu_preempt11:48:010
87956993621,5cyclictest131rcu_preempt11:27:020
87956993619,11cyclictest131rcu_preempt10:11:530
87956993618,4cyclictest131rcu_preempt08:31:240
87971993527,4cyclictest0-21swapper/312:10:273
87971993527,4cyclictest0-21swapper/311:40:163
87971993527,4cyclictest0-21swapper/308:45:003
87965993526,6cyclictest0-21swapper/208:20:012
87960993527,4cyclictest0-21swapper/108:55:171
87960993526,4cyclictest0-21swapper/111:25:171
87960993526,4cyclictest0-21swapper/109:10:271
87960993526,4cyclictest0-21swapper/107:30:001
87956993527,4cyclictest0-21swapper/012:14:590
87956993526,7cyclictest121ktimers/010:40:120
87956993521,4cyclictest131rcu_preempt11:56:250
87956993518,4cyclictest173122-21kworker/u8:0-events_freezable_power_11:32:090
87956993515,5cyclictest131rcu_preempt11:05:240
87956993512,13cyclictest131rcu_preempt09:50:220
87971993427,4cyclictest105741-21cron07:59:593
87971993427,4cyclictest105741-21cron07:59:593
87971993424,6cyclictest0-21swapper/307:35:263
87965993426,4cyclictest0-21swapper/211:35:252
87960993426,4cyclictest0-21swapper/109:55:181
87960993426,4cyclictest0-21swapper/109:55:171
87960993425,4cyclictest0-21swapper/109:35:191
87960993424,6cyclictest0-21swapper/107:25:011
87956993422,5cyclictest131rcu_preempt09:25:010
87956993421,8cyclictest121ktimers/012:20:260
87956993421,4cyclictest131rcu_preempt09:31:420
87956993420,6cyclictest131rcu_preempt10:50:510
87956993417,5cyclictest131rcu_preempt09:03:200
87956993415,10cyclictest131rcu_preempt09:05:240
87971993325,4cyclictest0-21swapper/310:50:173
8796599335,5cyclictest131rcu_preempt09:50:132
8796599333,7cyclictest131rcu_preempt07:40:112
8795699339,7cyclictest11-21ksoftirqd/010:25:270
87956993322,4cyclictest131rcu_preempt12:09:250
87956993318,4cyclictest131rcu_preempt12:38:010
87956993315,4cyclictest131rcu_preempt11:52:340
87956993315,10cyclictest131rcu_preempt08:52:090
87956993313,9cyclictest131rcu_preempt07:15:290
87956993311,12cyclictest131rcu_preempt08:40:210
87971993224,4cyclictest0-21swapper/312:00:173
87971993224,4cyclictest0-21swapper/312:00:173
87971993222,6cyclictest0-21swapper/309:15:013
8796599327,5cyclictest131rcu_preempt10:10:122
87965993223,5cyclictest0-21swapper/209:45:272
87965993223,4cyclictest0-21swapper/208:00:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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