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2026-02-27 - 15:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot6.osadl.org (updated Fri Feb 27, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911080,39ptp4l401ktimersoftd/307:48:053
82162930,3sleep09-21ksoftirqd/011:43:350
177642700,4sleep1120699cyclictest09:32:561
106891700,1ptp4l401ktimersoftd/311:13:503
228652670,2sleep20-21swapper/210:53:102
313882654,10sleep20-21swapper/207:47:452
206172620,2sleep020618-21ssh10:18:070
212712580,4sleep3401ktimersoftd/308:32:523
107832580,4sleep310778-21if_enp1s009:17:563
106891580,1ptp4l401ktimersoftd/312:28:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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