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2026-02-07 - 21:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Sat Feb 07, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1344521770,3sleep02113599cyclictest12:56:550
2674521570,4sleep32115299cyclictest12:04:343
1608321540,3sleep22114599cyclictest09:41:562
522921520,4sleep22114599cyclictest11:10:172
1068911050,4ptp4l401ktimersoftd/307:36:583
272552770,3sleep3401ktimersoftd/310:59:183
109932710,4sleep310994-21ssh12:21:403
172952670,2sleep30-21swapper/310:16:503
126502620,1sleep10-21swapper/110:44:381
42972590,5sleep02113599cyclictest11:08:420
169862590,4sleep22114599cyclictest11:54:412
252762580,1sleep00-21swapper/011:30:550
21145995846,7cyclictest33-21ksoftirqd/212:26:522
104562580,5sleep12113999cyclictest09:31:521
2115299570,23cyclictest17876-21awk12:27:093
21135995729,4cyclictest9-21ksoftirqd/013:06:410
289592550,3sleep22114599cyclictest07:56:342
21135995528,4cyclictest9-21ksoftirqd/008:06:340
21139995224,4cyclictest25-21ksoftirqd/111:21:561
21139995123,4cyclictest25-21ksoftirqd/112:51:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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