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2026-02-08 - 13:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Sun Feb 08, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2990921460,3sleep3266999cyclictest22:15:003
1068911170,9ptp4l32279-21kworker/3:019:37:093
106891670,1ptp4l401ktimersoftd/300:03:113
248042650,2sleep30-21swapper/322:42:103
248042650,2sleep30-21swapper/322:42:103
226132630,2sleep10-21swapper/100:17:231
226132630,2sleep10-21swapper/100:17:231
2652996049,5cyclictest25-21ksoftirqd/100:02:081
200722600,5sleep220074-21phc2sys23:42:152
70392580,1sleep20-21swapper/200:35:392
22602584,43sleep00-21swapper/019:38:110
106891580,1ptp4l401ktimersoftd/322:47:193
106891580,1ptp4l401ktimersoftd/300:23:113
106891580,1ptp4l401ktimersoftd/300:23:113
2652995745,5cyclictest25-21ksoftirqd/100:57:091
264799578,8cyclictest3382-21sed21:47:220
264512570,4sleep2266399cyclictest23:17:062
106891570,1ptp4l401ktimersoftd/322:33:203
264799557,7cyclictest26029-21tr00:22:080
264799557,7cyclictest26029-21tr00:22:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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