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2026-01-27 - 22:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Tue Jan 27, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2630122620,17sleep0111rcuc/007:30:570
1068911010,4ptp4l401ktimersoftd/307:33:303
294142870,2sleep00-21swapper/012:28:570
284392720,5sleep128442-21proc_pri07:35:501
141232710,2sleep20-21swapper/212:45:532
27020996956,7cyclictest25-21ksoftirqd/112:35:451
90272650,4sleep1241ktimersoftd/109:55:491
135372650,2sleep30-21swapper/312:45:503
27020995846,5cyclictest25-21ksoftirqd/112:45:471
27020995751,3cyclictest15060-21ssh10:35:431
27036995545,5cyclictest41-21ksoftirqd/307:35:403
27036995544,6cyclictest41-21ksoftirqd/308:05:403
2702899554,11cyclictest29657-21gpgconf10:50:322
27036995445,4cyclictest41-21ksoftirqd/311:50:443
27036995445,4cyclictest41-21ksoftirqd/311:50:443
268742544,37sleep10-21swapper/107:34:581
2702899537,7cyclictest2199-21latency_hist10:55:322
2702899532,12cyclictest2919-21latency_hist09:50:302
106891530,1ptp4l401ktimersoftd/308:24:143
103312530,2sleep20-21swapper/208:05:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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