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2026-02-08 - 21:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Sun Feb 08, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3031621770,4sleep01891099cyclictest12:11:590
1333021750,5sleep21892199cyclictest12:27:262
1333021750,5sleep21892199cyclictest12:27:262
2050021640,4sleep31893099cyclictest07:42:313
1068911020,3ptp4l401ktimersoftd/307:39:173
183332790,5sleep1241ktimersoftd/107:37:361
120722680,2sleep2311rcuc/209:42:092
266702670,9sleep2321ktimersoftd/207:57:072
185752664,9sleep00-21swapper/007:39:060
292162580,2sleep30-21swapper/312:10:053
176012580,2sleep30-21swapper/311:57:443
298242540,2sleep10-21swapper/112:11:071
12772530,2sleep30-21swapper/309:17:293
198942490,3sleep01891099cyclictest08:47:350
1893099477,7cyclictest41-21ksoftirqd/311:18:333
18930994718,9cyclictest41-21ksoftirqd/312:42:323
18930994624,9cyclictest41-21ksoftirqd/312:52:303
18930994522,9cyclictest41-21ksoftirqd/309:12:093
18930994422,8cyclictest41-21ksoftirqd/308:52:243
18930994422,10cyclictest41-21ksoftirqd/312:17:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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