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2026-02-20 - 07:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Fri Feb 20, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
988421460,4sleep33141499cyclictest00:26:353
1991021450,4sleep13140099cyclictest20:28:491
1068911090,4ptp4l401ktimersoftd/319:43:433
112762750,2sleep00-21swapper/023:53:360
262932710,3sleep10-21swapper/100:43:551
312842644,10sleep00-21swapper/019:48:220
242442640,2sleep30-21swapper/323:32:113
239792640,5sleep33141499cyclictest22:22:013
31395996251,5cyclictest9-21ksoftirqd/022:08:440
31395995744,6cyclictest9-21ksoftirqd/000:38:480
243032550,2sleep20-21swapper/222:57:372
131162540,3sleep125-21ksoftirqd/100:29:061
31414995224,10cyclictest41-21ksoftirqd/300:13:353
31414995223,9cyclictest41-21ksoftirqd/320:33:553
31414995223,10cyclictest41-21ksoftirqd/300:48:363
31414995222,9cyclictest41-21ksoftirqd/322:08:553
31414995221,7cyclictest41-21ksoftirqd/300:43:063
31400995225,7cyclictest25-21ksoftirqd/100:24:061
31400995224,7cyclictest25-21ksoftirqd/122:08:581
31414995123,10cyclictest41-21ksoftirqd/301:04:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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