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2026-01-16 - 00:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Thu Jan 15, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1207621750,3sleep12507799cyclictest12:06:571
2609721710,3sleep02507399cyclictest10:09:050
1091721660,3sleep12507799cyclictest12:39:131
2765621650,5sleep02507399cyclictest11:16:050
1068911210,8ptp4l21855-21kworker/3:007:26:453
106891820,1ptp4l401ktimersoftd/309:41:243
106891730,1ptp4l401ktimersoftd/310:50:263
106891720,1ptp4l401ktimersoftd/309:33:223
106891700,1ptp4l401ktimersoftd/309:54:093
253662670,2sleep30-21swapper/310:40:193
246732634,10sleep00-21swapper/007:24:560
106891620,1ptp4l401ktimersoftd/312:25:593
28222570,2sleep30-21swapper/312:30:083
118872550,2sleep20-21swapper/212:06:382
66662540,3sleep32508899cyclictest11:28:333
247102504,34sleep20-21swapper/207:25:262
172672500,2sleep30-21swapper/310:33:173
2507799480,4cyclictest18660-21diskmemload12:48:071
106891460,1ptp4l401ktimersoftd/312:23:133
106891440,10ptp4l401ktimersoftd/310:14:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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