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2026-02-25 - 09:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Wed Feb 25, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2604121660,3sleep0815899cyclictest23:21:370
2953021550,4sleep2817299cyclictest01:05:342
1969521350,4sleep0815899cyclictest23:47:510
1068911040,34ptp4l401ktimersoftd/319:49:593
64882807,55sleep00-21swapper/019:46:330
108832760,3sleep1241ktimersoftd/100:46:341
108832760,3sleep1241ktimersoftd/100:46:341
8163996352,5cyclictest25-21ksoftirqd/123:06:311
8181996210,13cyclictest21432-21fschecks_count20:16:323
61402600,2sleep10-21swapper/122:27:341
201282600,2sleep10-21swapper/123:48:361
197892600,4sleep119794-21missed_timers22:41:391
818199599,18cyclictest6492-21gltestperf00:41:393
818199599,18cyclictest6492-21gltestperf00:41:393
818199599,13cyclictest18336-21tr22:41:193
79902594,10sleep20-21swapper/219:50:302
818199589,13cyclictest29432-21cut00:31:403
8181995811,13cyclictest18621-21sed20:11:163
8181995810,11cyclictest11527-21sed21:01:443
8181995810,11cyclictest11527-21sed21:01:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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