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2026-01-24 - 17:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Sat Jan 24, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2676621610,4sleep1601999cyclictest10:34:091
1777121560,3sleep2602599cyclictest07:54:112
1068911090,4ptp4l401ktimersoftd/307:29:073
57412620,3sleep2311rcuc/212:55:542
6019996053,3cyclictest25-21ksoftirqd/111:14:041
58342594,10sleep10-21swapper/107:32:471
102102590,3sleep1601999cyclictest10:49:181
6019995648,4cyclictest25-21ksoftirqd/112:54:041
56352564,40sleep00-21swapper/007:30:110
6019995543,8cyclictest25-21ksoftirqd/111:35:361
303072550,2sleep20-21swapper/212:48:552
6019995444,4cyclictest25-21ksoftirqd/112:24:051
6019995343,6cyclictest25-21ksoftirqd/108:14:001
6019995242,5cyclictest25-21ksoftirqd/109:29:021
6019995142,5cyclictest25-21ksoftirqd/109:54:031
6019995141,5cyclictest25-21ksoftirqd/112:04:051
6019994837,5cyclictest25-21ksoftirqd/107:44:001
563224727,9sleep20-21swapper/207:30:092
179642470,2sleep30-21swapper/307:54:163
6032994616,7cyclictest41-21ksoftirqd/311:52:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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