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2026-02-10 - 14:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Tue Feb 10, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1103321730,5sleep13032199cyclictest00:48:141
1103321730,5sleep13032199cyclictest00:48:141
1442721710,3sleep13032199cyclictest22:05:091
1566521550,4sleep33033399cyclictest23:46:253
2664321530,4sleep13032199cyclictest23:58:151
1068911030,4ptp4l401ktimersoftd/319:39:373
303472820,2sleep00-21swapper/019:42:560
30316997158,5cyclictest9-21ksoftirqd/022:23:120
30316996956,6cyclictest9-21ksoftirqd/021:43:110
30316996955,7cyclictest9-21ksoftirqd/020:03:090
30316996754,5cyclictest9-21ksoftirqd/019:48:090
106891670,1ptp4l401ktimersoftd/322:31:343
30316996654,5cyclictest9-21ksoftirqd/000:08:160
105982660,2sleep00-21swapper/000:13:320
30316996556,5cyclictest9-21ksoftirqd/022:08:110
30316996553,5cyclictest9-21ksoftirqd/022:53:140
30316996553,5cyclictest9-21ksoftirqd/022:43:140
30316996450,7cyclictest9-21ksoftirqd/021:33:120
106891640,1ptp4l401ktimersoftd/321:46:023
30316996353,5cyclictest9-21ksoftirqd/001:08:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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