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2026-02-04 - 03:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Wed Feb 04, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911020,4ptp4l401ktimersoftd/319:37:063
25902840,1sleep30-21swapper/322:50:303
154572620,1sleep30-21swapper/300:42:153
96952580,2sleep10-21swapper/122:59:071
1798995822,15cyclictest41-21ksoftirqd/320:29:573
15182564,40sleep00-21swapper/019:37:320
1798995521,4cyclictest41-21ksoftirqd/320:12:513
13762554,10sleep10-21swapper/119:35:431
226772540,2sleep00-21swapper/023:10:580
1798995425,10cyclictest41-21ksoftirqd/300:04:593
1798995421,8cyclictest41-21ksoftirqd/322:14:533
1798995421,4cyclictest41-21ksoftirqd/300:49:333
182322530,1sleep30-21swapper/322:01:233
1798995325,4cyclictest41-21ksoftirqd/323:35:113
1798995324,5cyclictest41-21ksoftirqd/300:55:153
1798995323,5cyclictest41-21ksoftirqd/322:29:583
1798995225,9cyclictest41-21ksoftirqd/323:49:563
1798995224,9cyclictest41-21ksoftirqd/322:05:083
1798995224,10cyclictest41-21ksoftirqd/301:05:003
1798995224,10cyclictest41-21ksoftirqd/301:05:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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