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2026-02-19 - 19:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Thu Feb 19, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1709621740,4sleep02717899cyclictest10:17:490
2266021630,3sleep22718999cyclictest10:56:262
1068911200,8ptp4l12873-21kworker/3:107:48:033
27182997063,4cyclictest25-21ksoftirqd/110:48:281
106891690,1ptp4l401ktimersoftd/311:25:553
27182996862,3cyclictest25-21ksoftirqd/110:08:271
82832670,1sleep00-21swapper/012:22:560
106891670,1ptp4l401ktimersoftd/312:30:563
58632650,4sleep12718299cyclictest11:45:471
201292600,1sleep00-21swapper/012:33:480
267622584,42sleep00-21swapper/007:44:080
106891580,1ptp4l401ktimersoftd/311:51:053
5372570,3sleep12718299cyclictest11:07:371
219132570,3sleep20-21swapper/212:03:182
71882560,2sleep30-21swapper/310:39:363
27182995647,4cyclictest25-21ksoftirqd/111:58:291
27182995546,5cyclictest25-21ksoftirqd/112:58:311
27182995445,5cyclictest25-21ksoftirqd/113:08:311
27182995445,5cyclictest25-21ksoftirqd/111:28:291
27182995445,5cyclictest25-21ksoftirqd/109:53:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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