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2026-03-02 - 22:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Mon Mar 02, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2851421580,4sleep02115699cyclictest11:44:530
2221321560,4sleep02115699cyclictest07:54:360
243221510,3sleep32117599cyclictest11:51:543
1068911060,4ptp4l401ktimersoftd/307:49:533
50042600,5sleep22116699cyclictest08:24:412
21156995848,5cyclictest9-21ksoftirqd/009:34:320
21156995847,6cyclictest9-21ksoftirqd/008:39:330
21156995847,5cyclictest9-21ksoftirqd/009:44:340
210102574,41sleep10-21swapper/107:53:451
21156995646,5cyclictest9-21ksoftirqd/012:39:370
280892550,4sleep12116299cyclictest11:12:381
190672550,2sleep00-21swapper/007:49:320
212952530,5sleep22116699cyclictest09:59:442
21156995244,4cyclictest9-21ksoftirqd/011:29:350
21175995121,8cyclictest41-21ksoftirqd/312:54:473
21175995121,8cyclictest41-21ksoftirqd/312:54:473
21156995142,5cyclictest9-21ksoftirqd/010:29:320
208352514,35sleep20-21swapper/207:51:282
2117599496,7cyclictest41-21ksoftirqd/313:14:493
2117599494,7cyclictest41-21ksoftirqd/312:44:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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