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2026-02-10 - 01:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Mon Feb 09, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2443022890,3sleep30-21swapper/307:38:003
2443022890,3sleep30-21swapper/307:38:003
1560721350,5sleep32578199cyclictest11:51:083
76132710,1sleep00-21swapper/010:03:530
22172670,2sleep20-21swapper/207:57:572
255652644,10sleep00-21swapper/007:41:330
255652644,10sleep00-21swapper/007:41:330
240652630,3sleep2321ktimersoftd/211:27:062
25781996130,9cyclictest41-21ksoftirqd/312:48:043
25781995825,4cyclictest41-21ksoftirqd/310:23:063
25781995529,3cyclictest41-21ksoftirqd/310:33:013
25781995423,4cyclictest41-21ksoftirqd/310:21:083
255522514,35sleep20-21swapper/207:41:232
255522514,35sleep20-21swapper/207:41:232
25781995031,9cyclictest41-21ksoftirqd/310:08:133
25781995028,3cyclictest41-21ksoftirqd/311:52:583
25759995024,9cyclictest9-21ksoftirqd/012:38:130
25759995021,4cyclictest9-21ksoftirqd/009:53:010
25759995015,4cyclictest9-21ksoftirqd/011:55:010
25781994944,3cyclictest41-21ksoftirqd/308:42:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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