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2026-01-13 - 09:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Tue Jan 13, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
676121790,5sleep2304899cyclictest19:32:412
1676121590,3sleep0303699cyclictest21:48:200
106891990,3ptp4l401ktimersoftd/319:23:223
106891940,1ptp4l401ktimersoftd/300:48:563
80152630,5sleep3305499cyclictest23:18:003
235042580,3sleep3391rcuc/323:34:063
106891570,1ptp4l401ktimersoftd/322:58:303
106891570,1ptp4l401ktimersoftd/300:42:533
32452560,2sleep20-21swapper/221:35:452
32452560,2sleep20-21swapper/221:35:452
178882560,2sleep00-21swapper/000:34:370
303699544,17cyclictest8140-21/usr/sbin/munin22:12:490
196562540,2sleep30-21swapper/321:52:333
306212530,4sleep3305499cyclictest22:36:373
303699524,12cyclictest24685-21sed21:22:270
303699523,18cyclictest2543-21perl22:07:440
303699523,16cyclictest27813-21/usr/sbin/munin00:12:460
26922524,36sleep00-21swapper/019:24:150
304899504,42cyclictest2958-21latency_hist19:27:242
303699492,15cyclictest15492-21ssh23:27:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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