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2026-01-28 - 22:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot6.osadl.org (updated Wed Jan 28, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1068911690,4ptp4l401ktimersoftd/307:34:463
700329154,10sleep0121rcu_preempt07:31:230
144442810,19sleep233-21ksoftirqd/211:26:252
106891660,1ptp4l401ktimersoftd/310:21:263
8123996411,11cyclictest32736-21ls11:11:342
8133996350,6cyclictest41-21ksoftirqd/311:11:173
8123996312,10cyclictest18776-21latency_hist07:56:012
8123996311,14cyclictest22577-21grep08:01:222
106891630,1ptp4l401ktimersoftd/312:35:333
53342620,5sleep1811899cyclictest11:16:361
106891610,2ptp4l401ktimersoftd/311:00:403
8133996048,5cyclictest41-21ksoftirqd/310:11:153
8133996048,5cyclictest41-21ksoftirqd/310:11:153
302732600,4sleep3813399cyclictest10:36:313
8133995948,5cyclictest41-21ksoftirqd/310:46:173
8123995911,12cyclictest7073-21sed08:36:302
8123995911,12cyclictest4206-21cstates10:11:172
8123995911,12cyclictest4206-21cstates10:11:172
8123995911,11cyclictest18016-21gzip09:51:252
8123995911,10cyclictest23396-21cut10:31:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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