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2026-01-28 - 14:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot6.osadl.org (updated Wed Jan 28, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
359922840,4sleep30-21swapper/319:30:583
1785821820,4sleep3551699cyclictest21:55:173
122521630,5sleep0549799cyclictest22:11:040
278392720,2sleep30-21swapper/321:26:143
31722670,2sleep10-21swapper/123:51:061
5507996653,6cyclictest33-21ksoftirqd/200:01:002
167032650,3sleep2550799cyclictest00:37:082
159382650,5sleep233-21ksoftirqd/222:58:112
309502590,2sleep20-21swapper/200:51:172
5507995644,6cyclictest33-21ksoftirqd/220:00:552
5507995639,4cyclictest33-21ksoftirqd/223:16:002
290182560,1sleep20-21swapper/223:45:172
290182560,1sleep20-21swapper/223:45:172
244702560,2sleep20-21swapper/222:01:062
303782550,1sleep30-21swapper/300:18:543
18162530,2sleep30-21swapper/300:22:083
50962524,36sleep10-21swapper/119:31:541
551699510,2cyclictest9859-21ssh22:19:593
5507995141,5cyclictest33-21ksoftirqd/223:51:002
5507995022,3cyclictest33-21ksoftirqd/222:20:592
5507994941,4cyclictest33-21ksoftirqd/221:45:592
5507994938,6cyclictest33-21ksoftirqd/220:25:582
549799486,9cyclictest9-21ksoftirqd/023:36:380
249202480,1sleep124919-21ssh00:12:581
106891480,1ptp4l401ktimersoftd/322:26:313
5507994728,3cyclictest33-21ksoftirqd/223:31:052
549799477,9cyclictest9-21ksoftirqd/022:01:090
549799477,8cyclictest9-21ksoftirqd/000:31:210
549799476,9cyclictest9-21ksoftirqd/022:58:180
549799476,9cyclictest9-21ksoftirqd/000:19:180
549799476,11cyclictest9-21ksoftirqd/000:56:550
549799470,8cyclictest101ktimersoftd/022:16:030
5507994638,4cyclictest33-21ksoftirqd/223:01:002
5507994638,4cyclictest33-21ksoftirqd/200:45:562
5507994614,6cyclictest33-21ksoftirqd/221:40:592
549799466,9cyclictest9-21ksoftirqd/023:52:040
549799466,9cyclictest9-21ksoftirqd/022:47:050
549799466,9cyclictest9-21ksoftirqd/000:44:330
549799466,8cyclictest9-21ksoftirqd/022:41:010
549799466,10cyclictest9-21ksoftirqd/021:46:020
549799465,11cyclictest9-21ksoftirqd/023:46:450
549799456,9cyclictest9-21ksoftirqd/000:10:400
549799456,8cyclictest9-21ksoftirqd/022:39:430
549799456,7cyclictest9-21ksoftirqd/023:56:060
549799456,6cyclictest9-21ksoftirqd/021:51:010
549799456,6cyclictest9-21ksoftirqd/001:01:040
549799456,10cyclictest9-21ksoftirqd/023:11:220
549799455,7cyclictest9-21ksoftirqd/021:36:020
549799455,6cyclictest0-21swapper/020:36:040
549799455,10cyclictest9-21ksoftirqd/000:28:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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