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2026-02-05 - 08:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot6.osadl.org (updated Thu Feb 05, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3216121580,5sleep01956399cyclictest20:05:110
106891990,4ptp4l401ktimersoftd/319:39:283
46052760,2sleep00-21swapper/021:20:340
45042650,2sleep30-21swapper/323:41:493
45042650,2sleep30-21swapper/323:41:493
191592654,10sleep00-21swapper/019:36:190
107482600,1sleep00-21swapper/022:10:290
88422590,1sleep30-21swapper/320:20:393
33612570,2sleep30-21swapper/300:46:213
1957999546,9cyclictest33-21ksoftirqd/201:00:492
19579995342,3cyclictest33-21ksoftirqd/200:20:172
1957999527,10cyclictest33-21ksoftirqd/222:40:152
19579995224,4cyclictest33-21ksoftirqd/220:35:112
1958599511,13cyclictest8561-21turbostat00:20:163
1957999516,9cyclictest33-21ksoftirqd/223:10:272
1957999515,9cyclictest15384-21apt-get22:15:262
1957999514,8cyclictest33-21ksoftirqd/200:55:312
1957999514,7cyclictest33-21ksoftirqd/219:45:102
1957999513,8cyclictest24928-21munin-run19:50:102
19579995123,4cyclictest33-21ksoftirqd/200:22:042
1957999505,9cyclictest33-21ksoftirqd/223:05:352
1957999504,8cyclictest33-21ksoftirqd/222:30:432
1957999504,8cyclictest33-21ksoftirqd/222:00:132
1957999503,7cyclictest33-21ksoftirqd/200:35:382
19579995022,9cyclictest33-21ksoftirqd/223:57:302
19579995022,4cyclictest33-21ksoftirqd/220:45:292
1958599492,12cyclictest24325-21ssh01:08:453
1957999495,8cyclictest20741-21apt-get01:05:282
1957999494,9cyclictest33-21ksoftirqd/221:20:352
1957999494,7cyclictest33-21ksoftirqd/200:25:282
1957999493,9cyclictest33-21ksoftirqd/222:45:302
1957999493,9cyclictest33-21ksoftirqd/222:05:302
1957999492,7cyclictest33-21ksoftirqd/221:40:422
19579994921,4cyclictest33-21ksoftirqd/222:15:062
1958599483,13cyclictest30946-21ssh00:10:143
1958599480,12cyclictest22725-21sh22:55:273
1957999486,9cyclictest33-21ksoftirqd/220:15:272
1957999485,9cyclictest33-21ksoftirqd/220:00:272
1957999484,8cyclictest33-21ksoftirqd/223:00:282
1957999484,8cyclictest33-21ksoftirqd/222:45:142
1957999484,8cyclictest33-21ksoftirqd/200:50:182
1957999484,7cyclictest33-21ksoftirqd/223:20:512
1957999484,10cyclictest33-21ksoftirqd/222:50:332
1957999483,9cyclictest33-21ksoftirqd/221:35:122
1957999483,7cyclictest33-21ksoftirqd/221:05:262
1957999483,7cyclictest33-21ksoftirqd/220:55:292
1957999482,8cyclictest33-21ksoftirqd/221:45:292
1958599478,8cyclictest8785-21cat21:30:333
1958599478,7cyclictest41-21ksoftirqd/300:27:093
1958599477,8cyclictest41-21ksoftirqd/323:36:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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