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2026-01-26 - 13:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot6.osadl.org (updated Mon Jan 26, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3129821860,4sleep21785999cyclictest23:00:072
895921530,5sleep21785999cyclictest23:44:442
1204521490,3sleep21785999cyclictest22:07:442
953021480,5sleep01784899cyclictest21:30:000
1964521410,5sleep11785499cyclictest22:49:341
1068911000,38ptp4l401ktimersoftd/319:32:373
106891730,1ptp4l401ktimersoftd/321:53:513
106891710,1ptp4l401ktimersoftd/322:39:093
7682680,4sleep31786899cyclictest21:10:043
106891680,1ptp4l401ktimersoftd/321:44:413
191512660,2sleep10-21swapper/120:40:071
106891660,1ptp4l401ktimersoftd/322:48:043
106891660,1ptp4l401ktimersoftd/321:24:353
17854996533,3cyclictest25-21ksoftirqd/101:00:141
123082620,1sleep00-21swapper/021:34:580
106891620,1ptp4l401ktimersoftd/300:47:453
17854996049,5cyclictest25-21ksoftirqd/122:59:561
156012584,42sleep00-21swapper/019:29:430
86062570,5sleep01784899cyclictest23:10:090
174302564,10sleep20-21swapper/219:30:412
106891560,1ptp4l401ktimersoftd/300:17:573
106891560,1ptp4l401ktimersoftd/300:17:573
106891540,5ptp4l401ktimersoftd/322:09:073
106891540,1ptp4l401ktimersoftd/300:03:083
275762530,2sleep00-21swapper/000:35:130
17854995223,7cyclictest25-21ksoftirqd/122:55:111
106891520,3ptp4l23939-21kworker/3:100:53:043
17854995131,3cyclictest25-21ksoftirqd/122:05:031
106891510,1ptp4l401ktimersoftd/323:32:523
17854995025,13cyclictest25-21ksoftirqd/121:20:091
17854995023,5cyclictest25-21ksoftirqd/123:29:471
106891500,1ptp4l401ktimersoftd/319:54:523
17854994917,5cyclictest25-21ksoftirqd/122:35:081
17854994823,4cyclictest25-21ksoftirqd/100:19:481
17854994822,4cyclictest25-21ksoftirqd/122:15:021
152872480,1sleep00-21swapper/023:17:200
1785499477,7cyclictest25-21ksoftirqd/123:24:431
17854994723,4cyclictest25-21ksoftirqd/121:40:101
17854994723,4cyclictest25-21ksoftirqd/100:27:351
17854994723,4cyclictest25-21ksoftirqd/100:27:351
17854994625,7cyclictest25-21ksoftirqd/121:25:061
17854994617,4cyclictest25-21ksoftirqd/122:04:401
1785499456,3cyclictest25-21ksoftirqd/122:24:411
17854994539,3cyclictest25-21ksoftirqd/120:29:431
17854994531,3cyclictest25-21ksoftirqd/100:55:071
17854994521,3cyclictest25-21ksoftirqd/122:33:531
17854994520,4cyclictest25-21ksoftirqd/123:25:051
17854994520,4cyclictest25-21ksoftirqd/100:52:141
17854994520,3cyclictest25-21ksoftirqd/121:57:151
17854994517,9cyclictest25-21ksoftirqd/123:39:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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