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2026-01-20 - 23:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot6.osadl.org (updated Tue Jan 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1110322040,4sleep211106-21wc07:26:572
2500021650,3sleep21210999cyclictest12:02:162
1068911120,4ptp4l401ktimersoftd/307:26:523
200312760,2sleep10-21swapper/112:31:421
115382690,2sleep20-21swapper/209:36:552
323652660,5sleep01209699cyclictest11:37:010
323652660,5sleep01209699cyclictest11:37:010
132802650,2sleep00-21swapper/007:31:590
12117996523,8cyclictest41-21ksoftirqd/312:06:413
71542630,2sleep10-21swapper/112:17:091
245822610,3sleep224585-21cpuspeed_turbos10:56:522
119622614,45sleep00-21swapper/007:31:120
110512590,2sleep10-21swapper/112:55:311
12117995725,8cyclictest41-21ksoftirqd/311:56:523
176572550,2sleep10-21swapper/111:56:251
12109995544,6cyclictest33-21ksoftirqd/211:21:512
12117995424,7cyclictest41-21ksoftirqd/310:12:093
26082530,2sleep00-21swapper/012:12:300
186882530,2sleep20-21swapper/210:50:502
12117995234,3cyclictest41-21ksoftirqd/311:06:583
115962520,2sleep30-21swapper/311:49:203
12117995123,10cyclictest41-21ksoftirqd/310:16:543
12117995122,11cyclictest41-21ksoftirqd/309:11:373
12117995122,10cyclictest41-21ksoftirqd/310:01:513
12117995023,5cyclictest41-21ksoftirqd/312:32:043
12117995023,10cyclictest41-21ksoftirqd/309:56:533
12117995019,4cyclictest41-21ksoftirqd/310:36:583
12117994931,7cyclictest41-21ksoftirqd/312:41:423
12117994922,9cyclictest41-21ksoftirqd/310:51:523
12117994922,10cyclictest41-21ksoftirqd/308:31:503
12117994921,8cyclictest41-21ksoftirqd/308:42:043
1211799486,9cyclictest41-21ksoftirqd/311:41:553
1211799486,7cyclictest41-21ksoftirqd/311:16:433
1211799483,9cyclictest41-21ksoftirqd/312:11:513
12117994836,3cyclictest41-21ksoftirqd/308:01:553
12117994822,10cyclictest41-21ksoftirqd/310:25:383
12117994821,8cyclictest41-21ksoftirqd/309:01:373
12117994820,4cyclictest41-21ksoftirqd/310:44:003
12117994820,4cyclictest41-21ksoftirqd/310:27:493
12117994820,10cyclictest41-21ksoftirqd/312:59:593
12117994819,9cyclictest41-21ksoftirqd/312:08:233
12117994721,9cyclictest41-21ksoftirqd/309:41:503
1211799471,8cyclictest41-21ksoftirqd/312:52:013
12117994718,8cyclictest41-21ksoftirqd/311:41:403
12117994718,8cyclictest41-21ksoftirqd/311:41:403
12117994717,7cyclictest41-21ksoftirqd/312:47:393
12117994717,7cyclictest41-21ksoftirqd/309:52:403
12117994717,7cyclictest41-21ksoftirqd/309:52:403
12117994717,10cyclictest41-21ksoftirqd/311:22:013
12096994734,7cyclictest9-21ksoftirqd/010:01:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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