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2026-02-22 - 16:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot6.osadl.org (updated Sun Feb 22, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1968721520,3sleep23248899cyclictest09:35:142
3205821480,3sleep13248299cyclictest08:54:541
2302121440,2sleep13248299cyclictest12:38:241
1068911220,8ptp4l18199-21kworker/3:007:46:093
3096321090,8sleep125-21ksoftirqd/107:45:101
263982900,2sleep00-21swapper/012:07:040
32497997156,6cyclictest41-21ksoftirqd/310:10:073
32497996956,6cyclictest41-21ksoftirqd/313:05:123
32497996752,7cyclictest41-21ksoftirqd/309:15:053
32497996352,5cyclictest41-21ksoftirqd/307:55:043
119752630,1sleep20-21swapper/211:51:442
119752630,1sleep20-21swapper/211:51:442
32497996049,5cyclictest41-21ksoftirqd/310:05:073
32497996049,5cyclictest41-21ksoftirqd/308:25:073
32497995951,4cyclictest41-21ksoftirqd/312:45:103
321832594,43sleep00-21swapper/007:47:240
106891590,1ptp4l401ktimersoftd/311:50:283
106891590,1ptp4l401ktimersoftd/311:50:283
121892570,4sleep341-21ksoftirqd/312:25:463
106891570,1ptp4l401ktimersoftd/312:04:153
32497995645,5cyclictest41-21ksoftirqd/308:05:083
32497995645,5cyclictest41-21ksoftirqd/308:05:083
274272550,2sleep10-21swapper/108:45:061
106891550,1ptp4l401ktimersoftd/311:17:473
32497995341,6cyclictest41-21ksoftirqd/308:15:053
32482995213,5cyclictest25-21ksoftirqd/111:36:531
32497994936,5cyclictest41-21ksoftirqd/310:40:073
105791490,4getstats3249799cyclictest08:55:503
3248299482,17cyclictest25619-21diskmemload12:58:121
3248299482,13cyclictest0-21swapper/111:34:031
32482994812,6cyclictest25-21ksoftirqd/108:34:381
218662470,2sleep00-21swapper/012:02:260
106891470,2ptp4l14290-21kworker/3:112:56:113
106891470,2ptp4l14290-21kworker/3:111:24:333
3248299465,6cyclictest25236-21rm10:56:101
32497994539,3cyclictest41-21ksoftirqd/313:15:033
32497994514,8cyclictest41-21ksoftirqd/310:35:233
32497994434,4cyclictest41-21ksoftirqd/308:00:063
32497994434,4cyclictest41-21ksoftirqd/308:00:063
3248299448,5cyclictest25-21ksoftirqd/111:55:101
32497994336,4cyclictest41-21ksoftirqd/308:49:583
32497994319,4cyclictest41-21ksoftirqd/310:15:153
3248299437,5cyclictest25-21ksoftirqd/111:50:111
3248299437,5cyclictest25-21ksoftirqd/111:50:111
3248299425,5cyclictest25-21ksoftirqd/110:27:171
3249799410,8cyclictest41-21ksoftirqd/310:55:243
32497994030,5cyclictest41-21ksoftirqd/309:30:083
32497994029,4cyclictest41-21ksoftirqd/309:45:073
32497994027,3cyclictest41-21ksoftirqd/311:35:213
32497994015,15cyclictest41-21ksoftirqd/309:40:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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