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2026-02-16 - 09:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Feb 16, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238521387,94sleep12439-21fschecks_time19:02:301
238521387,94sleep12439-21fschecks_time19:02:301
2223212414,91sleep00-21swapper/019:02:210
2223212414,91sleep00-21swapper/019:02:210
36749911953,8cyclictest0-21swapper/019:37:020
36749911953,8cyclictest0-21swapper/019:37:020
36749911948,17cyclictest3666-21cyclictest21:55:140
36749911635,11cyclictest0-21swapper/021:27:040
129621140,7sleep00-21swapper/000:27:170
36749911336,19cyclictest3786-21cut21:47:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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