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2026-01-17 - 03:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 17, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9977991193,54cyclictest25874-21kworker/u18:0+rpciod00:09:191
954421196,16sleep00-21swapper/019:05:290
9977991163,77cyclictest7502-21apt-get23:34:151
99779911364,14cyclictest8588-21kworker/u17:0+events_unbound20:58:591
99779911364,14cyclictest8588-21kworker/u17:0+events_unbound20:58:591
99779911010,82cyclictest9045-21ssh21:49:171
99779910363,18cyclictest181rcu_preempt19:24:241
99779910363,18cyclictest181rcu_preempt19:24:241
980929713,51sleep19840-21modprobe19:09:001
9972999670,20cyclictest28434-21latency_hist20:04:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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