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2026-01-19 - 13:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Jan 19, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244119911451,56cyclictest518-21fschecks_count22:04:111
23915211420,76sleep30-21swapper/319:04:403
23915211420,76sleep30-21swapper/319:04:403
24411991123,44cyclictest25922-21apt-get19:14:061
244119910548,9cyclictest0-21swapper/122:19:301
2341129529,36sleep20-21swapper/219:04:262
2341129529,36sleep20-21swapper/219:04:262
126842950,6sleep30-21swapper/320:09:213
2440799943,63cyclictest26855-21apt-get19:14:070
24411999269,15cyclictest26324-21kworker/u19:0-rpciod23:48:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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