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2026-02-01 - 14:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Feb 01, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288959911556,51cyclictest298-21in:imuxsock19:13:010
288959911556,51cyclictest298-21in:imuxsock19:13:010
28909991126,92cyclictest19878-21apt-get00:18:241
28895991123,99cyclictest0-21swapper/022:23:150
289179910925,40cyclictest29914-21ls20:48:032
289179910925,40cyclictest29914-21ls20:48:032
289099910778,22cyclictest19743-21sh22:28:221
289099910778,22cyclictest19743-21sh22:28:221
28895991052,70cyclictest16724-21dpkg23:18:010
288959910517,68cyclictest4356-21kworker/u17:3+rpciod22:12:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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