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2026-01-22 - 05:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Jan 22, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189809911043,10cyclictest0-21swapper/120:29:161
189809911043,10cyclictest0-21swapper/120:29:161
189809910438,12cyclictest0-21swapper/122:49:051
18980991023,33cyclictest18982-21latency_hist19:08:441
189809910136,7cyclictest0-21swapper/120:14:441
18984999945,13cyclictest18967-21cyclictest00:04:162
18984999945,13cyclictest18967-21cyclictest00:04:162
18980999933,12cyclictest0-21swapper/119:50:001
1898099983,45cyclictest20127-21apt-get20:48:521
18980999742,8cyclictest0-21swapper/122:28:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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