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2026-02-08 - 22:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Feb 08, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2173499118102,8cyclictest0-21swapper/009:18:010
21593210517,60sleep021621-21munin-run07:07:310
21734991042,85cyclictest26412-21kworker/u19:1+ext4-rsv-conversion12:17:510
2084221018,63sleep120890-21ps07:03:121
1722921000,6sleep10-21swapper/108:32:331
1722921000,6sleep10-21swapper/108:32:331
21756999732,11cyclictest0-21swapper/211:08:052
2175699972,51cyclictest14002-21wc11:23:042
2175699972,51cyclictest14002-21wc11:23:042
2175699972,38cyclictest18889-21grep12:23:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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