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2026-03-08 - 07:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Mar 08, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147359912160,11cyclictest0-21swapper/222:55:582
13713210913,66sleep013229-21/usr/sbin/munin19:01:170
13713210913,66sleep013229-21/usr/sbin/munin19:01:170
142592946,17sleep20-21swapper/219:01:392
142592946,17sleep20-21swapper/219:01:392
14735999161,9cyclictest181rcu_preempt00:21:032
14722999171,9cyclictest14710-21cyclictest23:01:260
109892910,4sleep1301ktimers/100:21:171
67022900,8sleep30-21swapper/322:26:223
67022900,8sleep30-21swapper/322:26:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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