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2026-01-15 - 15:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Jan 15, 2026 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23947210512,62sleep223994-21basename07:09:062
241179910485,13cyclictest6944-21kworker/u17:1-nfsiod09:44:311
241179910475,21cyclictest31050-21diskmemload10:54:091
2411799992,65cyclictest8164-21apt-get09:24:251
2411799992,65cyclictest8164-21apt-get09:24:251
24108999663,26cyclictest0-21swapper/010:29:220
24108999663,26cyclictest0-21swapper/010:29:220
24125999574,12cyclictest0-21swapper/211:04:282
24125999478,9cyclictest0-21swapper/207:09:402
24125999469,19cyclictest6729-21latency_hist07:54:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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