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2026-02-22 - 06:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Feb 22, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2545122240,62sleep239-21ksoftirqd/219:02:102
2545122240,62sleep239-21ksoftirqd/219:02:102
26481991224,89cyclictest26019-21apt-get22:41:552
2775421100,8sleep10-21swapper/123:38:191
26481999863,12cyclictest181rcu_preempt00:21:392
26481999863,12cyclictest181rcu_preempt00:21:392
26469999563,26cyclictest277-21dbus-daemon00:01:380
26476999359,7cyclictest181rcu_preempt00:24:191
26481999248,18cyclictest181rcu_preempt00:32:032
26481999248,18cyclictest181rcu_preempt00:32:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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