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2026-03-04 - 16:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Mar 04, 2026 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306179912550,25cyclictest30604-21cyclictest10:21:240
2914621238,85sleep10-21swapper/107:01:101
306329911244,36cyclictest30604-21cyclictest11:49:212
2011321100,5sleep30-21swapper/310:22:293
306179910150,9cyclictest181rcu_preempt10:53:320
3029121016,15sleep20-21swapper/207:03:442
30632999830,35cyclictest0-21swapper/210:20:562
30632999266,20cyclictest24505-21latency_hist10:30:582
30627999169,14cyclictest30604-21cyclictest11:25:541
30627999164,19cyclictest352-21runrttasks07:51:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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