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2026-01-16 - 03:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Fri Jan 16, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10183991182,29cyclictest28567-21seq20:01:250
10183991152,26cyclictest9673-21ssh23:37:130
10183991152,21cyclictest30524-21ssh23:18:080
10183991122,25cyclictest17800-21sh22:02:170
10183991122,25cyclictest17800-21sh22:02:170
10183991114,29cyclictest352-21runrttasks00:08:100
10183991093,29cyclictest352-21runrttasks23:05:030
10183991093,29cyclictest352-21runrttasks00:27:020
10183991092,25cyclictest30043-21seq20:04:450
101839910853,51cyclictest10174-21cyclictest21:09:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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