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2026-01-17 - 17:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 17, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307479912652,53cyclictest28360-21ssh11:34:190
29320211413,66sleep029333-21grep07:04:230
307839911140,34cyclictest7883-21sh11:54:172
30747991105,28cyclictest352-21runrttasks11:28:370
30747991083,38cyclictest5643-21runrttasks09:09:100
30747991082,25cyclictest12389-21sendmail_mailtr09:19:310
30747991064,27cyclictest352-21runrttasks10:17:320
30747991064,27cyclictest352-21runrttasks10:17:320
30747991063,42cyclictest31044-21apt-get07:09:300
30747991062,26cyclictest23345-21ssh12:19:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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