You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-20 - 03:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Tue Jan 20, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
700221890,12sleep26962-21grep19:08:512
700221890,12sleep26962-21grep19:08:512
7087991252,25cyclictest32133-21/usr/sbin/munin20:24:280
7087991252,25cyclictest32133-21/usr/sbin/munin20:24:280
7087991203,88cyclictest352-21runrttasks22:17:520
7087991203,88cyclictest352-21runrttasks22:17:520
1841921200,4sleep218418-21if_err_eth022:09:152
7087991192,55cyclictest26342-21ssh21:29:040
70879911728,53cyclictest0-21swapper/000:23:200
7087991163,25cyclictest27489-21ssh00:12:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional