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2026-01-24 - 09:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 24, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3077921237,16sleep20-21swapper/219:03:422
322829911761,49cyclictest26356-21sh23:28:501
322829911761,49cyclictest26356-21sh23:28:501
32272991153,49cyclictest2827-21unixbench_singl21:54:090
322729911347,15cyclictest6709-21diskmemload23:01:230
322829911050,29cyclictest6681-21cron21:08:321
3142221088,70sleep131464-21/usr/sbin/munin19:04:141
322729910742,12cyclictest0-21swapper/021:08:320
32161210310,64sleep032172-21systemd-run19:08:330
322829910238,12cyclictest0-21swapper/119:19:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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