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2026-01-30 - 06:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Fri Jan 30, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298269911758,53cyclictest20790-21fschecks_time23:23:310
29826991133,32cyclictest21003-21fschecks_time00:18:300
29826991123,31cyclictest29831-21latency_hist19:08:130
298269910937,61cyclictest0-21swapper/020:18:370
29826991073,31cyclictest14714-21/usr/sbin/munin00:08:240
29826991073,31cyclictest14714-21/usr/sbin/munin00:08:240
298269910645,56cyclictest0-21swapper/021:13:350
298269910644,56cyclictest17967-21kernelversion20:08:350
298269910644,56cyclictest17967-21kernelversion20:08:350
29826991063,28cyclictest7084-21ssh23:54:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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