You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-30 - 18:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Fri Jan 30, 2026 12:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11429991163,94cyclictest5889-21apt-get08:28:270
1031021087,63sleep110374-21latency07:03:391
114299910347,16cyclictest181rcu_preempt09:08:100
114299910347,16cyclictest181rcu_preempt09:08:100
114389910249,46cyclictest23898-21proc_pri11:03:372
114389910249,46cyclictest23898-21proc_pri11:03:372
114389910136,15cyclictest0-21swapper/208:28:502
11434991014,72cyclictest9726-21apt-get12:28:251
11429991013,74cyclictest9726-21apt-get12:28:360
11438991003,36cyclictest13682-21modprobe08:53:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional