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2026-01-24 - 15:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 24, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
375211717,71sleep2406-21systemd-run07:08:332
160612960,6sleep20-21swapper/210:14:042
554999448,15cyclictest181rcu_preempt10:43:332
554999448,15cyclictest181rcu_preempt10:43:332
543999371,16cyclictest8688-21fschecks_time09:08:510
549999139,17cyclictest181rcu_preempt12:03:461
549999139,17cyclictest181rcu_preempt12:03:461
543999121,26cyclictest0-21swapper/009:59:120
543999121,26cyclictest0-21swapper/009:59:120
554999058,9cyclictest181rcu_preempt08:34:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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