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2026-01-21 - 04:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Jan 21, 2026 00:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18709991352,97cyclictest29824-21apt-get23:04:001
186999911658,9cyclictest16057-21switchtime22:39:190
186999911658,9cyclictest16057-21switchtime22:39:190
18709991133,87cyclictest14356-21apt-get21:43:591
186999911354,15cyclictest298-21in:imuxsock19:43:440
186999911354,15cyclictest298-21in:imuxsock19:43:440
187099910630,44cyclictest0-21swapper/122:49:131
18709991053,90cyclictest30599-21cat23:58:471
18709991053,90cyclictest30599-21cat23:58:471
2607021040,6sleep10-21swapper/122:56:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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