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2026-02-26 - 23:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Feb 26, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149029912460,57cyclictest20581-21latency_hist07:21:220
149029912046,65cyclictest10823-21sh08:31:190
149029912046,65cyclictest10823-21sh08:31:190
14902991154,56cyclictest87-21kswapd011:17:130
149029911530,10cyclictest0-21swapper/008:21:510
149029911445,62cyclictest0-21swapper/007:46:580
149029911344,61cyclictest2729-21diskmemload09:26:360
1329221138,79sleep20-21swapper/207:01:312
1329221138,79sleep20-21swapper/207:01:312
149029911238,8cyclictest0-21swapper/011:16:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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