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2026-03-05 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Mar 05, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4782991493,98cyclictest16672-21apt-get23:01:102
4782991493,98cyclictest16672-21apt-get23:01:102
4773991232,36cyclictest15773-21swap21:11:270
4773991193,10cyclictest0-21swapper/019:05:570
47739911553,52cyclictest0-21swapper/019:45:550
47739911553,52cyclictest0-21swapper/019:45:550
47739911314,28cyclictest28243-21taskset23:20:060
47739911252,53cyclictest15031-21latency_hist19:35:570
4773991113,27cyclictest1461-21apt-get22:36:090
4773991113,27cyclictest1461-21apt-get22:36:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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