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2026-02-07 - 22:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Feb 07, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20123214811,24sleep10-21swapper/107:03:191
20838991013,72cyclictest8846-21taskset08:07:511
2005329914,62sleep019339-21/usr/sbin/munin07:03:180
20838999556,14cyclictest181rcu_preempt09:31:291
20838999556,14cyclictest181rcu_preempt09:31:291
20838999252,10cyclictest181rcu_preempt08:52:381
20833999267,17cyclictest1874-21sh07:47:340
20833999267,17cyclictest1874-21sh07:47:340
2083399913,65cyclictest8836-21apt-get08:07:590
2083399913,65cyclictest23897-21ssh10:47:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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