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2026-01-31 - 13:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 31, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1390599136118,12cyclictest12173-21apt-get00:28:570
119121210,6sleep30-21swapper/320:08:053
119121210,6sleep30-21swapper/320:08:053
13905991186,42cyclictest13535-21ssh22:43:180
139059911749,60cyclictest0-21swapper/022:38:290
139059911723,11cyclictest0-21swapper/019:08:080
139059911445,62cyclictest0-21swapper/021:53:380
13905991124,29cyclictest13140-21/usr/sbin/munin21:48:290
13905991114,43cyclictest20312-21latency_hist23:48:200
13905991103,34cyclictest8375-21fschecks_time23:28:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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