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2026-02-16 - 15:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Feb 16, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1549221620,21sleep20-21swapper/207:02:482
1568921166,16sleep00-21swapper/007:05:150
160909911458,49cyclictest0-21swapper/010:11:590
160909911458,49cyclictest0-21swapper/010:11:590
161019911142,39cyclictest352-21runrttasks11:30:431
16090991094,31cyclictest24308-21sh09:07:410
161019910864,38cyclictest30320-21idleruntime11:07:201
3064721040,27sleep230650-21proc_pri11:07:292
161099910459,37cyclictest0-21swapper/207:57:002
16090991043,28cyclictest17979-21fschecks_time09:52:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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