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2026-02-15 - 20:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Feb 15, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24804991322,119cyclictest26565-21apt-get09:52:250
2350921229,75sleep223552-21fschecks_time07:02:312
24804991153,88cyclictest32011-21apt-get11:47:190
248049911424,43cyclictest0-21swapper/010:17:050
248049910935,68cyclictest0-21swapper/011:32:150
248049910841,60cyclictest0-21swapper/011:07:350
248049910841,60cyclictest0-21swapper/011:07:350
248099910741,13cyclictest0-21swapper/110:22:291
248049910739,60cyclictest17209-21ssh10:29:160
24804991073,85cyclictest10330-21ssh11:12:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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