You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-03 - 01:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Mar 02, 2026 12:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263109911646,62cyclictest8847-21sh12:01:060
26310991164,11cyclictest0-21swapper/007:06:080
26310991153,26cyclictest5974-21sh09:12:350
263109911452,56cyclictest277-21dbus-daemon08:46:050
26310991133,31cyclictest1762-21diskmemload09:06:240
26310991122,24cyclictest6852-21rm10:08:510
263109911136,48cyclictest1246-21diskmemload10:21:310
26310991112,28cyclictest20792-21taskset12:20:350
263109911041,62cyclictest0-21swapper/011:06:360
26310991103,30cyclictest352-21runrttasks12:04:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional