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2026-02-14 - 19:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Feb 14, 2026 12:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1578321169,77sleep115850-21latency07:02:391
169229911059,45cyclictest23949-21threads09:03:162
1288421060,5sleep30-21swapper/309:40:213
169229910255,40cyclictest5680-21/usr/sbin/munin12:12:222
169229910237,34cyclictest0-21swapper/210:27:212
16922991003,63cyclictest22781-21ssh09:57:222
169229910031,37cyclictest0-21swapper/208:54:072
16903999970,20cyclictest19984-21fschecks_count09:52:280
16903999970,20cyclictest19984-21fschecks_count09:52:280
116202980,6sleep00-21swapper/011:27:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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