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2026-02-17 - 04:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Tue Feb 17, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21035213113,82sleep121074-21cut19:02:241
224759912860,8cyclictest0-21swapper/000:12:000
224759912860,8cyclictest0-21swapper/000:12:000
224869912558,57cyclictest352-21runrttasks22:07:281
224869912558,57cyclictest352-21runrttasks22:07:281
224869911960,52cyclictest22456-21cyclictest22:47:351
224759911657,14cyclictest22456-21cyclictest21:21:590
22486991083,54cyclictest20877-21kworker/u19:1+ext4-rsv-conversion21:12:131
2614221010,7sleep30-21swapper/321:55:543
224869910138,10cyclictest0-21swapper/121:21:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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