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2026-02-18 - 05:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Feb 18, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
900225810,16sleep00-21swapper/019:02:140
225199992,73cyclictest19749-21runrttasks19:57:232
225199992,73cyclictest19749-21runrttasks19:57:232
2251999553,35cyclictest0-21swapper/200:17:312
2251999553,35cyclictest0-21swapper/200:17:312
223599953,66cyclictest7938-21apt-get19:22:070
223599953,66cyclictest7938-21apt-get19:22:070
225199943,53cyclictest21920-21apt-get21:27:072
12622948,55sleep21294-21/usr/sbin/munin19:02:292
93129323,32sleep10-21swapper/119:02:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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