You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-09 - 23:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Feb 09, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2609521529,21sleep00-21swapper/007:02:490
27431991152,71cyclictest14193-21taskset10:22:462
27431991152,71cyclictest14193-21taskset10:22:462
274319911142,13cyclictest0-21swapper/208:02:292
274319910244,12cyclictest5034-21kworker/u17:1-rpciod12:26:362
27424999558,16cyclictest28443-21kworker/u17:1+xprtiod10:29:220
27431999465,19cyclictest10820-21latency_hist10:17:302
27431999449,9cyclictest24248-21kworker/u17:3-rpciod10:44:022
27431999449,9cyclictest24248-21kworker/u17:3-rpciod10:44:022
27431999449,13cyclictest1737-21kworker/u17:2-events_unbound07:43:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional