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2026-02-22 - 19:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Feb 22, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23600220114,30sleep00-21swapper/007:02:000
249159910590,10cyclictest29721-21kworker/u18:2-rpciod11:31:592
249159910590,10cyclictest29721-21kworker/u18:2-rpciod11:31:592
249109910556,8cyclictest181rcu_preempt07:12:141
249109910556,8cyclictest181rcu_preempt07:12:141
249059910282,9cyclictest26864-21apt-get10:47:010
2407029411,44sleep10-21swapper/107:02:181
129172940,6sleep10-21swapper/110:22:131
24915999231,10cyclictest181rcu_preempt09:51:512
24915999231,10cyclictest181rcu_preempt09:51:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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