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2026-02-28 - 00:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Fri Feb 27, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156252990,6sleep20-21swapper/209:56:402
156252990,6sleep20-21swapper/209:56:402
10013999973,17cyclictest14651-21ntp_kernel_pll_08:56:442
10004999455,16cyclictest181rcu_preempt12:12:410
10013999355,13cyclictest181rcu_preempt10:58:542
10013999165,17cyclictest29444-21timerandwakeup12:06:502
10013998963,17cyclictest298-21in:imuxsock08:26:152
10013998963,17cyclictest298-21in:imuxsock08:26:152
10013998853,11cyclictest181rcu_preempt11:41:372
10013998853,11cyclictest181rcu_preempt11:41:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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