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2026-01-21 - 23:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Jan 21, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14570212012,71sleep014584-21grep07:04:150
14570212012,71sleep014584-21grep07:04:150
14325210811,69sleep20-21swapper/207:04:042
14325210811,69sleep20-21swapper/207:04:042
15697991043,34cyclictest10086-21runrttasks08:29:011
2852021030,5sleep00-21swapper/011:04:410
15697991023,63cyclictest21376-21apt-get10:53:531
156919910065,23cyclictest26009-21apt-get07:38:570
156919910065,23cyclictest26009-21apt-get07:38:570
15697999979,12cyclictest0-21swapper/112:29:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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