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2026-02-02 - 07:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Feb 02, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11121991283,26cyclictest18608-21/usr/sbin/munin22:58:490
11121991277,11cyclictest0-21swapper/022:16:190
111219911158,47cyclictest15173-21sh22:53:170
111219911048,54cyclictest12902-21unixbench_multi22:48:330
11121991083,29cyclictest9672-21wc23:38:090
11121991083,29cyclictest9672-21wc23:38:090
11121991082,34cyclictest13248-21cat00:37:590
11121991082,34cyclictest13248-21cat00:37:590
11121991082,20cyclictest16348-21seq22:01:500
11121991056,10cyclictest0-21swapper/019:08:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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