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2026-01-29 - 05:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Jan 29, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12767210415,64sleep012765-21munin-run19:08:160
12852999361,11cyclictest181rcu_preempt21:58:390
12852999361,11cyclictest181rcu_preempt21:58:390
1285299932,59cyclictest18364-21apt-get23:48:270
12859999159,16cyclictest29129-21ssh21:23:282
12852999159,10cyclictest181rcu_preempt22:43:230
12859998955,12cyclictest181rcu_preempt19:13:152
12859998946,9cyclictest23017-21ssh23:00:432
12852998955,24cyclictest16607-21latency_hist19:18:150
12859998846,13cyclictest181rcu_preempt22:06:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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