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2026-02-03 - 20:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Tue Feb 03, 2026 00:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27621991062,78cyclictest10325-21chrt00:03:250
276279910234,12cyclictest0-21swapper/122:15:221
276279910039,9cyclictest0-21swapper/122:03:051
27627999942,49cyclictest0-21swapper/120:18:221
27627999848,44cyclictest0-21swapper/120:57:531
2762799983,35cyclictest3953-21ssh23:53:031
27630999725,30cyclictest3915-21ssh23:52:592
2762799964,31cyclictest8354-21latency_hist21:17:551
27627999630,12cyclictest0-21swapper/100:33:271
27627999630,12cyclictest0-21swapper/100:33:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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