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2026-02-21 - 06:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sat Feb 21, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19930215110,95sleep019373-21/usr/sbin/munin19:02:180
19564213513,80sleep119620-21sort19:02:071
210149912448,68cyclictest0-21swapper/023:37:090
20864212411,78sleep220867-21apt-key19:06:452
210149912247,11cyclictest0-21swapper/022:51:440
210149911951,8cyclictest0-21swapper/000:27:140
210149911250,12cyclictest28959-21unixbench_singl23:52:470
210379910948,54cyclictest27765-21diskmemload00:07:151
210379910948,54cyclictest27765-21diskmemload00:07:151
210379910253,42cyclictest0-21swapper/100:31:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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