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2026-02-23 - 22:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Mon Feb 23, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
320319911828,80cyclictest0-21swapper/010:11:340
31193211825,72sleep30-21swapper/307:02:163
31193211825,72sleep30-21swapper/307:02:163
32031991154,34cyclictest22710-21/usr/sbin/munin11:22:060
32031991126,28cyclictest19209-21modprobe12:01:520
32031991113,32cyclictest352-21runrttasks12:08:280
32031991062,31cyclictest28304-21seq09:41:550
32031991053,25cyclictest13021-21fschecks_count09:16:540
320319910516,10cyclictest0-21swapper/008:11:530
32031991043,29cyclictest28292-21latency_hist10:36:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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