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2026-01-18 - 17:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Sun Jan 18, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15972991313,60cyclictest11973-21ssh12:29:080
159729912351,12cyclictest0-21swapper/009:04:160
159729912351,12cyclictest0-21swapper/009:04:160
15986991176,67cyclictest32287-21diskmemload12:09:082
2609121050,7sleep10-21swapper/110:10:331
2609121050,7sleep10-21swapper/110:10:331
159869910452,13cyclictest2453-21kworker/u17:2-xprtiod12:34:162
159869910452,13cyclictest2453-21kworker/u17:2-xprtiod12:34:162
158312996,15sleep20-21swapper/207:08:492
1598699986,64cyclictest12228-21apt-get08:39:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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