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2026-03-05 - 17:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Thu Mar 05, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
955521349,99sleep09567-21apt-get07:01:020
11022991223,81cyclictest5446-21apt-get10:31:081
11022991093,92cyclictest25697-21apt-get10:11:071
110229910262,17cyclictest181rcu_preempt09:50:561
110229910262,17cyclictest181rcu_preempt09:50:561
110229910252,11cyclictest181rcu_preempt11:55:011
11022999762,13cyclictest181rcu_preempt12:28:051
11018999764,21cyclictest14699-21ssh10:46:060
105772976,17sleep10-21swapper/107:01:451
271802960,6sleep30-21swapper/307:51:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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