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2026-02-04 - 21:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Feb 04, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243019910971,13cyclictest181rcu_preempt09:57:452
243019910971,13cyclictest181rcu_preempt09:57:452
2712321040,7sleep30-21swapper/311:43:193
243019910442,35cyclictest24270-21cyclictest10:38:102
243019910442,35cyclictest24270-21cyclictest10:38:102
23597210334,34sleep00-21swapper/007:03:330
243019910240,30cyclictest0-21swapper/210:03:022
243019910240,30cyclictest0-21swapper/210:03:022
95122990,7sleep20-21swapper/211:13:032
24301999659,13cyclictest181rcu_preempt07:33:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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