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2026-04-12 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot7.osadl.org (updated Sun Apr 12, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2887217312,127sleep12920-21cut06:58:451
43519912048,48cyclictest29861-21apt-get11:23:360
43699910164,7cyclictest181rcu_preempt09:08:242
43699910164,7cyclictest181rcu_preempt09:08:242
43519910064,9cyclictest181rcu_preempt11:18:420
4369999776,12cyclictest0-21swapper/207:03:252
4369999573,15cyclictest17842-21kworker/u17:0-xprtiod11:33:532
4362999467,18cyclictest4319-21cyclictest08:03:231
4362999154,7cyclictest181rcu_preempt09:13:051
4362999152,11cyclictest181rcu_preempt09:20:341
4369999043,9cyclictest181rcu_preempt07:18:322
4369999043,9cyclictest181rcu_preempt07:18:322
4362999068,9cyclictest0-21swapper/107:53:201
4351999047,10cyclictest181rcu_preempt07:43:340
4351999047,10cyclictest181rcu_preempt07:43:340
408529014,49sleep04106-21systemd-run07:03:210
4362998962,11cyclictest181rcu_preempt12:29:441
4362998962,11cyclictest181rcu_preempt12:29:441
4351998951,24cyclictest32408-21ssh12:21:250
4351998951,24cyclictest32408-21ssh12:21:250
4369998874,7cyclictest0-21swapper/209:13:462
4369998866,12cyclictest0-21swapper/211:13:552
4351998866,15cyclictest4319-21cyclictest07:38:480
4351998860,8cyclictest181rcu_preempt10:58:280
4351998860,8cyclictest181rcu_preempt10:58:280
4351998837,7cyclictest181rcu_preempt11:08:300
4351998837,7cyclictest181rcu_preempt11:08:300
4369998771,10cyclictest11890-21kworker/u17:1-xprtiod11:47:072
4369998771,10cyclictest11890-21kworker/u17:1-xprtiod11:47:072
4369998762,13cyclictest0-21swapper/210:48:532
4369998762,13cyclictest0-21swapper/210:48:532
4362998764,13cyclictest0-21swapper/109:38:471
4351998739,14cyclictest181rcu_preempt11:17:090
4369998671,8cyclictest0-21swapper/209:48:512
4369998666,11cyclictest0-21swapper/212:28:372
4369998666,11cyclictest0-21swapper/212:28:372
4362998663,13cyclictest0-21swapper/112:13:421
4362998562,12cyclictest0-21swapper/111:58:221
4362998554,11cyclictest181rcu_preempt11:43:221
4362998546,7cyclictest181rcu_preempt10:23:221
4362998546,7cyclictest181rcu_preempt10:23:221
4351998564,17cyclictest4319-21cyclictest11:30:580
4351998553,12cyclictest181rcu_preempt07:53:580
4351998538,35cyclictest27843-21modprobe08:13:200
4351998538,35cyclictest27843-21modprobe08:13:200
4369998453,9cyclictest181rcu_preempt10:43:482
4369998452,8cyclictest181rcu_preempt07:30:102
4369998441,8cyclictest181rcu_preempt07:08:412
4369998438,19cyclictest15882-21kworker/u18:1-events_unbound11:10:192
4369998438,19cyclictest15882-21kworker/u18:1-events_unbound11:10:192
4369998432,11cyclictest181rcu_preempt10:23:322
4362998463,12cyclictest0-21swapper/111:03:551
4362998461,16cyclictest297-21systemd-logind09:33:201
4351998451,16cyclictest181rcu_preempt10:48:120
4351998449,7cyclictest181rcu_preempt10:03:090
4351998449,7cyclictest181rcu_preempt10:03:090
4351998437,16cyclictest0-21swapper/010:09:100
4351998437,16cyclictest0-21swapper/010:09:100
4369998366,8cyclictest0-21swapper/212:03:402
4369998354,13cyclictest181rcu_preempt09:23:352
4362998365,13cyclictest10156-21unixbench_multi09:53:551
4362998363,14cyclictest14727-21latency_hist10:03:241
4362998363,14cyclictest14727-21latency_hist10:03:241
4362998362,12cyclictest0-21swapper/110:43:451
4362998351,8cyclictest181rcu_preempt11:12:541
4362998351,8cyclictest181rcu_preempt11:12:541
4362998329,19cyclictest0-21swapper/107:08:241
4362998329,19cyclictest0-21swapper/107:08:241
4351998358,19cyclictest12511-21sh09:03:500
4351998358,19cyclictest12511-21sh09:03:500
4351998353,25cyclictest0-21swapper/011:58:190
4351998352,23cyclictest10025-21latency_hist08:58:220
4351998348,14cyclictest181rcu_preempt07:04:370
4351998348,14cyclictest181rcu_preempt07:04:370
4351998346,7cyclictest181rcu_preempt12:08:210
4351998345,7cyclictest181rcu_preempt08:48:500
4351998322,17cyclictest0-21swapper/010:53:560
4369998261,11cyclictest0-21swapper/209:58:482
4369998261,11cyclictest0-21swapper/209:58:482
4362998262,13cyclictest0-21swapper/109:13:541
4362998261,12cyclictest0-21swapper/110:58:441
4362998261,12cyclictest0-21swapper/110:58:441
4362998248,7cyclictest181rcu_preempt07:22:341
4362998248,7cyclictest181rcu_preempt07:22:341
4362998246,9cyclictest181rcu_preempt08:28:201
4362998240,30cyclictest22774-21modprobe07:58:201
4351998247,7cyclictest181rcu_preempt09:43:470
4351998241,8cyclictest181rcu_preempt08:58:430
4369998167,8cyclictest0-21swapper/209:18:522
4369998162,9cyclictest0-21swapper/208:08:202
4369998161,11cyclictest0-21swapper/208:33:562
4369998161,11cyclictest0-21swapper/208:33:562
4369998160,11cyclictest0-21swapper/208:43:522
4369998157,11cyclictest0-21swapper/208:23:442
4369998141,9cyclictest181rcu_preempt11:23:492
4369998138,18cyclictest6056-21runrttasks10:42:572
4369998138,18cyclictest6056-21runrttasks10:42:572
4369998130,7cyclictest181rcu_preempt11:38:342
4362998160,11cyclictest0-21swapper/110:32:271
4362998157,13cyclictest0-21swapper/107:28:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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