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2026-01-05 - 02:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot7.osadl.org (updated Sun Jan 04, 2026 12:44:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
713991133,69cyclictest3165-21apt-get07:15:151
7139910860,12cyclictest22589-21ssh10:23:291
2936921080,6sleep20-21swapper/208:35:062
31021056,17sleep20-21swapper/207:06:522
60429918,57sleep0617-21systemd-run07:09:510
713999566,15cyclictest181rcu_preempt12:17:591
717999355,9cyclictest181rcu_preempt11:41:312
717999165,13cyclictest0-21swapper/210:00:122
713999156,7cyclictest181rcu_preempt08:15:271
713999140,19cyclictest2418-21grep08:50:181
713999132,15cyclictest0-21swapper/108:20:111
717999070,13cyclictest8097-21diskmemload11:29:492
713999050,13cyclictest181rcu_preempt10:35:001
713999029,15cyclictest0-21swapper/112:06:091
713998971,12cyclictest20084-21switchtime11:10:251
713998849,9cyclictest181rcu_preempt07:25:221
72199873,61cyclictest14739-21taskset07:50:153
3189328715,37sleep10-21swapper/107:05:161
717998668,9cyclictest0-21swapper/207:24:512
717998665,12cyclictest0-21swapper/208:14:512
717998665,12cyclictest0-21swapper/208:14:512
717998650,7cyclictest181rcu_preempt11:37:522
713998663,15cyclictest291rcuc/110:10:191
713998639,14cyclictest0-21swapper/109:14:591
713998635,31cyclictest0-21swapper/111:20:121
72199855,41cyclictest0-21swapper/310:10:293
713998561,8cyclictest181rcu_preempt12:39:021
713998561,8cyclictest181rcu_preempt12:39:021
713998559,8cyclictest181rcu_preempt08:14:511
713998559,8cyclictest181rcu_preempt08:14:511
713998548,8cyclictest181rcu_preempt10:49:511
713998548,8cyclictest181rcu_preempt10:49:511
713998538,12cyclictest12264-21ssh11:50:071
713998538,12cyclictest12264-21ssh11:50:071
713998536,13cyclictest700-21cyclictest08:25:121
713998532,22cyclictest700-21cyclictest07:40:271
713998530,13cyclictest0-21swapper/110:55:151
709998570,8cyclictest0-21swapper/010:15:280
717998464,12cyclictest0-21swapper/207:55:152
717998458,16cyclictest25501-21/usr/sbin/munin11:20:172
717998410,35cyclictest39-21ksoftirqd/211:12:482
713998436,26cyclictest700-21cyclictest09:51:401
713998426,36cyclictest0-21swapper/111:34:181
72199834,40cyclictest0-21swapper/308:45:203
717998365,8cyclictest0-21swapper/208:59:522
717998365,8cyclictest0-21swapper/208:59:522
717998346,8cyclictest181rcu_preempt10:06:442
713998340,21cyclictest5097-21idleruntime07:20:141
713998338,14cyclictest700-21cyclictest12:21:461
713998331,27cyclictest0-21swapper/111:41:521
71399832,53cyclictest32725-21apt-get08:45:191
713998320,31cyclictest0-21swapper/107:30:221
709998311,14cyclictest13752-21chrt11:51:510
709998311,14cyclictest13752-21chrt11:51:510
72199823,46cyclictest0-21swapper/312:30:183
717998260,15cyclictest24414-21sh09:35:102
717998249,26cyclictest16830-21kworker/u19:2+nfsiod11:45:462
71799822,31cyclictest39-21ksoftirqd/210:20:162
713998260,13cyclictest8621-21ssh10:00:291
713998253,12cyclictest181rcu_preempt09:57:431
713998253,12cyclictest181rcu_preempt09:57:431
713998251,8cyclictest181rcu_preempt07:50:261
713998249,12cyclictest181rcu_preempt11:02:261
713998249,12cyclictest181rcu_preempt11:02:261
717998166,8cyclictest0-21swapper/209:25:072
717998165,8cyclictest0-21swapper/212:05:172
717998165,8cyclictest0-21swapper/208:05:122
717998158,14cyclictest31653-21kworker/u18:2+events_unbound07:44:512
717998149,10cyclictest181rcu_preempt09:46:232
717998144,9cyclictest181rcu_preempt11:56:502
713998152,12cyclictest181rcu_preempt12:30:571
713998150,8cyclictest181rcu_preempt11:19:521
713998146,13cyclictest181rcu_preempt09:00:141
713998146,12cyclictest181rcu_preempt10:05:321
713998145,9cyclictest181rcu_preempt11:35:091
713998144,8cyclictest181rcu_preempt10:54:111
713998142,12cyclictest27066-21latency10:30:181
713998142,12cyclictest27066-21latency10:30:181
713998051,8cyclictest181rcu_preempt11:45:211
713998049,9cyclictest181rcu_preempt11:25:051
713998045,8cyclictest181rcu_preempt07:55:361
713998044,8cyclictest181rcu_preempt10:27:141
713998042,8cyclictest181rcu_preempt11:58:301
72199793,33cyclictest12439-21chrt09:15:253
717997951,9cyclictest181rcu_preempt12:04:482
717997951,9cyclictest181rcu_preempt12:04:482
717997945,7cyclictest181rcu_preempt12:19:282
717997942,7cyclictest181rcu_preempt08:20:062
713997939,12cyclictest1581-21switchtime07:10:241
713997931,30cyclictest0-21swapper/110:42:241
713997930,21cyclictest0-21swapper/110:15:161
713997930,13cyclictest0-21swapper/111:05:421
713997911,21cyclictest291rcuc/108:40:191
72199783,34cyclictest13418-21chrt10:09:463
717997863,8cyclictest0-21swapper/212:30:482
717997848,7cyclictest181rcu_preempt10:38:152
717997847,21cyclictest24136-21sh08:19:492
717997834,14cyclictest181rcu_preempt10:42:282
713997851,13cyclictest181rcu_preempt09:36:061
713997844,7cyclictest181rcu_preempt09:44:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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