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2026-02-04 - 18:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot7.osadl.org (updated Wed Feb 04, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243019910971,13cyclictest181rcu_preempt09:57:452
243019910971,13cyclictest181rcu_preempt09:57:452
2712321040,7sleep30-21swapper/311:43:193
243019910442,35cyclictest24270-21cyclictest10:38:102
243019910442,35cyclictest24270-21cyclictest10:38:102
23597210334,34sleep00-21swapper/007:03:330
243019910240,30cyclictest0-21swapper/210:03:022
243019910240,30cyclictest0-21swapper/210:03:022
95122990,7sleep20-21swapper/211:13:032
24301999659,13cyclictest181rcu_preempt07:33:062
24301999654,21cyclictest181rcu_preempt11:08:152
320902950,4sleep0241irq_work/010:56:230
24301999468,10cyclictest181rcu_preempt07:23:042
24301999433,28cyclictest0-21swapper/209:48:052
24279999467,14cyclictest0-21swapper/011:12:500
24279999372,13cyclictest0-21swapper/008:03:090
24289999275,9cyclictest0-21swapper/107:12:501
24289999266,17cyclictest0-21swapper/111:43:081
24279999273,9cyclictest0-21swapper/008:58:090
24279999268,13cyclictest0-21swapper/011:53:500
24301999141,20cyclictest1148-21timerwakeupswit11:54:042
24301999052,15cyclictest181rcu_preempt11:59:042
24301999028,30cyclictest0-21swapper/212:28:232
24301999026,28cyclictest24270-21cyclictest08:26:582
24279999062,9cyclictest181rcu_preempt08:47:580
24307998914,42cyclictest0-21swapper/309:43:073
24301998953,16cyclictest181rcu_preempt10:23:182
24301998953,16cyclictest181rcu_preempt10:23:182
24279998964,17cyclictest3646-21kernelversion10:08:120
24301998851,16cyclictest181rcu_preempt12:37:412
24301998851,14cyclictest181rcu_preempt10:51:412
24301998828,19cyclictest0-21swapper/212:15:552
24301998758,10cyclictest181rcu_preempt12:03:592
24301998752,12cyclictest181rcu_preempt11:29:202
24301998745,12cyclictest181rcu_preempt12:22:222
24301998732,20cyclictest0-21swapper/207:58:142
24301998727,25cyclictest0-21swapper/211:00:252
24279998771,9cyclictest0-21swapper/009:53:120
24279998771,9cyclictest0-21swapper/009:53:120
24279998769,12cyclictest0-21swapper/007:43:220
24301998631,29cyclictest0-21swapper/207:08:112
24301998630,15cyclictest0-21swapper/208:33:162
24301998630,15cyclictest0-21swapper/208:33:162
24279998670,9cyclictest0-21swapper/009:12:500
24279998670,9cyclictest0-21swapper/007:38:190
24279998668,11cyclictest31201-21diskmemload09:19:270
24279998668,11cyclictest31201-21diskmemload09:19:270
24279998654,14cyclictest12590-21ssh09:29:410
24301998567,11cyclictest0-21swapper/207:53:422
24301998567,11cyclictest0-21swapper/207:53:422
24301998551,11cyclictest181rcu_preempt08:03:042
24301998527,10cyclictest0-21swapper/210:37:352
24279998569,9cyclictest0-21swapper/007:28:220
24301998441,14cyclictest181rcu_preempt08:52:482
24301998440,15cyclictest181rcu_preempt08:32:502
24301998437,25cyclictest19676-21snmpd10:02:502
24279998470,7cyclictest0-21swapper/011:33:090
24279998470,7cyclictest0-21swapper/011:33:090
24279998469,8cyclictest0-21swapper/012:13:240
24279998417,40cyclictest0-21swapper/010:42:490
24279998417,40cyclictest0-21swapper/010:42:490
24301998360,15cyclictest23152-21idleruntime-cro09:47:462
24301998346,9cyclictest181rcu_preempt07:43:092
24301998339,12cyclictest14086-21mailstats08:13:202
24301998336,24cyclictest23114-21latency_hist08:42:492
24301998336,24cyclictest23114-21latency_hist08:42:492
24301998328,10cyclictest0-21swapper/212:08:032
24301998328,10cyclictest0-21swapper/212:08:032
24289998368,8cyclictest0-21swapper/111:22:461
24289998363,13cyclictest0-21swapper/110:52:491
24289998363,11cyclictest0-21swapper/111:53:501
24279998355,19cyclictest0-21swapper/011:32:480
24279998325,37cyclictest0-21swapper/011:43:190
24301998238,7cyclictest181rcu_preempt10:18:522
24301998228,13cyclictest0-21swapper/207:12:562
24301998228,13cyclictest0-21swapper/207:12:562
24289998262,11cyclictest0-21swapper/110:53:171
24279998261,15cyclictest31201-21diskmemload12:18:100
24279998259,13cyclictest0-21swapper/011:23:130
24279998259,13cyclictest0-21swapper/011:23:130
24301998146,12cyclictest181rcu_preempt09:17:342
24301998146,10cyclictest181rcu_preempt09:37:502
24301998146,10cyclictest181rcu_preempt09:37:502
24301998133,11cyclictest0-21swapper/208:53:242
24301998132,10cyclictest0-21swapper/211:06:312
24301998127,30cyclictest0-21swapper/208:08:092
24279998122,30cyclictest15-21ksoftirqd/009:39:460
24279998111,35cyclictest15-21ksoftirqd/008:44:240
24279998111,35cyclictest15-21ksoftirqd/008:44:240
2421528111,43sleep124213-21munin-run07:07:501
24307998012,36cyclictest0-21swapper/310:03:373
24307998012,36cyclictest0-21swapper/310:03:373
24301998051,13cyclictest27488-21ssh11:43:482
24301998046,10cyclictest181rcu_preempt11:48:472
24301998039,12cyclictest31201-21diskmemload10:08:122
24289998061,8cyclictest0-21swapper/107:28:101
24279998058,12cyclictest0-21swapper/008:08:080
24301997947,10cyclictest181rcu_preempt10:13:232
24301997947,10cyclictest181rcu_preempt10:13:232
24301997945,9cyclictest181rcu_preempt11:36:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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