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2025-11-21 - 05:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Nov 21, 2025 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1733121038,70sleep20-21swapper/219:05:052
18283999967,16cyclictest0-21swapper/122:50:071
18283999876,13cyclictest10085-21latency_hist00:29:291
18274999874,14cyclictest9324-21cpu20:20:010
18274999874,14cyclictest9324-21cpu20:20:010
18274999777,11cyclictest0-21swapper/019:29:500
18283999638,35cyclictest0-21swapper/122:43:221
18283999638,35cyclictest0-21swapper/122:43:221
1728029611,59sleep017313-21ntp_kernel_pll_19:05:030
1828399953,60cyclictest15980-21apt-get20:39:421
18274999572,13cyclictest0-21swapper/023:14:490
18274999572,13cyclictest0-21swapper/023:14:490
18274999572,12cyclictest0-21swapper/019:49:310
18283999444,16cyclictest181rcu_preempt20:05:281
18274999473,12cyclictest0-21swapper/020:04:490
18274999472,13cyclictest0-21swapper/022:20:040
18283999254,16cyclictest181rcu_preempt19:14:541
18283999254,16cyclictest181rcu_preempt19:14:541
18283999049,13cyclictest181rcu_preempt19:34:541
18283999038,10cyclictest181rcu_preempt23:54:271
18283999038,10cyclictest181rcu_preempt23:54:271
18274999076,8cyclictest0-21swapper/023:10:040
18274999073,7cyclictest0-21swapper/019:25:010
18283998954,8cyclictest181rcu_preempt21:13:011
18283998935,11cyclictest8662-21fschecks_count21:35:491
18274998952,8cyclictest181rcu_preempt22:18:200
18274998952,8cyclictest181rcu_preempt22:18:200
18274998875,7cyclictest0-21swapper/000:14:290
18283998738,28cyclictest20200-21timerandwakeup20:50:031
18283998730,32cyclictest0-21swapper/120:14:551
18274998620,36cyclictest15-21ksoftirqd/000:30:460
1685528610,36sleep10-21swapper/119:04:481
18283998561,17cyclictest26599-21latency_hist23:04:301
18283998561,16cyclictest0-21swapper/100:09:291
18283998561,16cyclictest0-21swapper/100:09:291
18283998540,16cyclictest1188-21fschecks_time19:54:501
18283998533,23cyclictest18260-21cyclictest20:45:051
18274998572,7cyclictest0-21swapper/019:09:510
18274998536,8cyclictest181rcu_preempt00:21:040
18283998459,10cyclictest181rcu_preempt22:49:301
18283998459,10cyclictest181rcu_preempt22:49:301
18283998432,26cyclictest0-21swapper/119:19:481
18274998454,8cyclictest181rcu_preempt23:26:340
18283998355,13cyclictest181rcu_preempt23:24:551
18283998353,9cyclictest181rcu_preempt00:17:361
18283998353,13cyclictest181rcu_preempt00:22:191
18283998349,8cyclictest181rcu_preempt21:24:301
18283998349,8cyclictest181rcu_preempt20:34:531
18283998349,10cyclictest181rcu_preempt23:30:071
18283998349,10cyclictest181rcu_preempt23:30:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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