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2026-07-14 - 10:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Tue Jul 14, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31306213513,84sleep031339-21munin-run18:57:050
31306213513,84sleep031339-21munin-run18:57:050
314729911444,13cyclictest0-21swapper/120:52:261
305412999,62sleep230559-21pluginstate18:52:472
305412999,62sleep230559-21pluginstate18:52:472
272942980,7sleep10-21swapper/123:19:451
3147299978,64cyclictest8229-21apt-get23:42:211
31472999327,25cyclictest0-21swapper/120:22:071
31467999370,17cyclictest277-21dbus-daemon20:57:070
31467999278,8cyclictest0-21swapper/023:42:070
31467999278,8cyclictest0-21swapper/023:42:070
3146799913,54cyclictest15-21ksoftirqd/023:32:240
31472999078,8cyclictest0-21swapper/122:56:281
31472999078,8cyclictest0-21swapper/122:56:281
31467998870,12cyclictest277-21dbus-daemon21:22:050
31479998772,9cyclictest16153-21sh23:02:032
31479998663,11cyclictest0-21swapper/221:12:272
31479998657,8cyclictest181rcu_preempt23:13:312
31467998672,7cyclictest0-21swapper/021:47:240
31467998667,9cyclictest0-21swapper/022:22:080
31479998568,11cyclictest11085-21ntpd22:33:222
31479998564,9cyclictest0-21swapper/222:02:082
31479998557,7cyclictest181rcu_preempt00:03:052
31467998572,7cyclictest0-21swapper/019:22:220
31479998465,9cyclictest0-21swapper/222:17:422
31479998464,10cyclictest0-21swapper/223:08:412
31479998464,10cyclictest0-21swapper/223:08:412
31479998464,10cyclictest0-21swapper/220:52:062
31479998452,10cyclictest181rcu_preempt20:59:562
31467998469,9cyclictest14082-21vmstat22:02:450
31467998465,9cyclictest0-21swapper/019:27:280
31479998368,9cyclictest23812-21kworker/u17:3-xprtiod21:52:072
31479998363,10cyclictest0-21swapper/220:22:082
31472998335,13cyclictest181rcu_preempt21:52:131
31472998335,13cyclictest181rcu_preempt21:52:131
31467998359,17cyclictest31454-21cyclictest21:52:470
31467998359,17cyclictest31454-21cyclictest21:52:470
3146799834,44cyclictest15-21ksoftirqd/022:58:130
31479998266,9cyclictest0-21swapper/219:27:062
31479998265,10cyclictest27735-21kworker/u17:0-xprtiod23:42:052
31479998265,10cyclictest27735-21kworker/u17:0-xprtiod23:42:052
31479998262,12cyclictest298-21in:imuxsock19:48:042
31479998261,10cyclictest0-21swapper/219:02:072
31479998261,10cyclictest0-21swapper/219:02:072
31472998255,15cyclictest0-21swapper/123:47:451
31472998255,15cyclictest0-21swapper/123:47:451
31472998254,19cyclictest8447-21xargs19:22:401
31479998163,9cyclictest0-21swapper/220:27:072
31479998161,9cyclictest0-21swapper/221:28:202
3147999812,48cyclictest39-21ksoftirqd/222:49:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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