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2026-01-29 - 09:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Thu Jan 29, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12767210415,64sleep012765-21munin-run19:08:160
12852999361,11cyclictest181rcu_preempt21:58:390
12852999361,11cyclictest181rcu_preempt21:58:390
1285299932,59cyclictest18364-21apt-get23:48:270
12859999159,16cyclictest29129-21ssh21:23:282
12852999159,10cyclictest181rcu_preempt22:43:230
12859998955,12cyclictest181rcu_preempt19:13:152
12859998946,9cyclictest23017-21ssh23:00:432
12852998955,24cyclictest16607-21latency_hist19:18:150
12859998846,13cyclictest181rcu_preempt22:06:232
12859998753,15cyclictest18241-21ssh22:53:262
12856998766,15cyclictest31665-21switchtime00:08:461
12852998759,8cyclictest181rcu_preempt00:33:150
1285699862,38cyclictest31-21ksoftirqd/120:53:451
12852998562,17cyclictest29513-21kernelversion21:23:370
12852998554,21cyclictest11901-21latency_hist20:43:150
12852998546,19cyclictest181rcu_preempt23:09:140
12852998546,19cyclictest181rcu_preempt23:09:140
12859998442,11cyclictest181rcu_preempt00:23:292
12852998458,8cyclictest181rcu_preempt23:53:320
12859998342,14cyclictest23183-21/usr/sbin/munin19:38:382
12859998342,14cyclictest23183-21/usr/sbin/munin19:38:382
12859998341,11cyclictest181rcu_preempt22:43:272
12859998340,8cyclictest181rcu_preempt22:18:262
12859998336,13cyclictest181rcu_preempt21:11:562
12852998345,30cyclictest15-21ksoftirqd/019:38:150
12852998342,12cyclictest58-21kcompactd022:40:090
12859998264,12cyclictest30617-21kernelversion23:13:382
12859998244,8cyclictest181rcu_preempt19:28:152
12859998244,8cyclictest181rcu_preempt19:28:152
12859998236,12cyclictest181rcu_preempt23:43:372
12852998261,15cyclictest27106-21latency_hist23:08:150
12852998251,12cyclictest181rcu_preempt23:45:420
12859998158,17cyclictest544-21cron20:58:132
12859998144,13cyclictest6880-21ssh23:28:292
12856998164,10cyclictest5497-21ssh23:25:411
12856998112,45cyclictest31-21ksoftirqd/123:46:011
12852998158,15cyclictest200-21systemd-journal23:26:320
12852998150,11cyclictest181rcu_preempt00:07:270
12852998142,25cyclictest28526-21ssh22:15:370
12859998058,15cyclictest12841-21cyclictest00:03:342
12859998057,15cyclictest19787-21diskmemload00:30:402
12859998037,9cyclictest181rcu_preempt23:23:402
12859998030,21cyclictest0-21swapper/200:33:352
12859998030,21cyclictest0-21swapper/200:33:352
12856998064,10cyclictest21832-21kworker/u19:1-events_unbound21:23:161
1285699803,34cyclictest31-21ksoftirqd/121:53:151
1285699803,34cyclictest31-21ksoftirqd/121:53:151
1285699802,40cyclictest31-21ksoftirqd/121:43:291
1285699802,34cyclictest31-21ksoftirqd/120:15:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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