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2025-11-27 - 11:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Thu Nov 27, 2025 00:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
543821100,8sleep25398-21ssh23:44:402
2231521100,7sleep222299-21apt-get21:29:162
4465210411,66sleep14551-21/usr/sbin/munin19:04:491
5085991003,71cyclictest25207-21apt-get22:29:192
5069999959,8cyclictest181rcu_preempt22:44:390
493429812,47sleep04969-21munin-run19:09:040
48342947,66sleep20-21swapper/219:07:432
5085999161,10cyclictest181rcu_preempt21:49:152
5085999161,10cyclictest181rcu_preempt21:49:152
5069999167,15cyclictest0-21swapper/021:29:400
5085998869,12cyclictest5060-21cyclictest23:24:062
5069998852,15cyclictest19247-21/usr/sbin/munin23:15:260
5085998743,16cyclictest181rcu_preempt21:44:202
5069998766,14cyclictest24246-21kworker/u19:0-rpciod21:15:580
5069998766,14cyclictest24246-21kworker/u19:0-rpciod21:15:580
508599863,67cyclictest10602-21apt-get21:09:182
5069998653,8cyclictest181rcu_preempt23:56:070
5085998458,11cyclictest181rcu_preempt19:24:062
5069998447,8cyclictest181rcu_preempt20:29:150
5069998447,8cyclictest181rcu_preempt20:29:150
5069998447,13cyclictest12240-21latency_hist19:29:060
5085998313,10cyclictest0-21swapper/222:44:192
5069998345,8cyclictest0-21swapper/020:04:360
5085998257,17cyclictest13861-21latency23:59:302
5085998257,17cyclictest13861-21latency23:59:302
5085998238,13cyclictest181rcu_preempt20:54:042
5085998230,27cyclictest0-21swapper/219:14:212
5085998224,25cyclictest0-21swapper/219:24:312
5069998254,8cyclictest181rcu_preempt21:49:010
5069998249,9cyclictest181rcu_preempt00:31:490
5069998248,11cyclictest181rcu_preempt21:49:250
5069998248,11cyclictest181rcu_preempt21:49:250
5085998167,10cyclictest5060-21cyclictest20:59:372
5085998167,10cyclictest5060-21cyclictest20:59:372
5085998152,21cyclictest316-21rs:main2
5085998135,13cyclictest181rcu_preempt22:22:212
5077998167,8cyclictest0-21swapper/123:44:331
5069998159,15cyclictest316-21rs:main0
5069998151,7cyclictest181rcu_preempt22:06:270
5085998065,11cyclictest5060-21cyclictest00:14:142
5085998050,10cyclictest181rcu_preempt00:04:182
5085998046,11cyclictest181rcu_preempt23:54:442
5085998039,13cyclictest181rcu_preempt21:19:252
5069998056,18cyclictest6731-21latency_hist19:14:060
5085997956,15cyclictest32152-21sh20:34:032
5085997956,15cyclictest32152-21sh20:34:032
5085997954,14cyclictest25608-21sh00:19:402
5085997911,33cyclictest39-21ksoftirqd/223:51:592
5069997959,13cyclictest25759-21netstat21:34:300
5085997861,10cyclictest13112-21latency_hist22:09:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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