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2026-03-05 - 23:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Thu Mar 05, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
955521349,99sleep09567-21apt-get07:01:020
11022991223,81cyclictest5446-21apt-get10:31:081
11022991093,92cyclictest25697-21apt-get10:11:071
110229910262,17cyclictest181rcu_preempt09:50:561
110229910262,17cyclictest181rcu_preempt09:50:561
110229910252,11cyclictest181rcu_preempt11:55:011
11022999762,13cyclictest181rcu_preempt12:28:051
11018999764,21cyclictest14699-21ssh10:46:060
105772976,17sleep10-21swapper/107:01:451
271802960,6sleep30-21swapper/307:51:263
17692950,5sleep20-21swapper/209:31:182
7282940,2sleep10-21swapper/108:11:161
11022999455,17cyclictest181rcu_preempt12:16:121
11022999442,21cyclictest11009-21cyclictest09:31:271
101872948,60sleep210234-21run-parts07:01:332
11027999275,11cyclictest16343-21apt-key09:00:532
11022999142,14cyclictest181rcu_preempt11:07:411
11018999175,10cyclictest30327-21ssh11:11:160
11027999069,15cyclictest29598-21timerandwakeup10:16:272
11018999033,34cyclictest6046-21timerandwakeup08:26:260
11022998763,10cyclictest181rcu_preempt09:06:061
11022998758,13cyclictest181rcu_preempt11:20:161
1102299862,30cyclictest17915-21ssh10:51:071
11018998662,18cyclictest10598-21ssh09:46:210
11018998655,7cyclictest181rcu_preempt09:21:560
11022998543,11cyclictest181rcu_preempt09:28:081
11022998543,11cyclictest181rcu_preempt09:28:081
11022998535,13cyclictest181rcu_preempt08:30:551
11022998528,34cyclictest0-21swapper/110:48:151
11022998523,28cyclictest0-21swapper/107:11:271
11022998457,18cyclictest16431-21apt-key09:00:541
11022998435,8cyclictest181rcu_preempt11:01:251
11022998357,9cyclictest181rcu_preempt10:36:361
11022998349,12cyclictest181rcu_preempt10:26:261
11022998349,12cyclictest181rcu_preempt10:26:261
11018998367,10cyclictest25832-21ssh10:11:250
11027998265,11cyclictest300-21rs:main2
11022998262,14cyclictest29428-21sh09:23:091
11022998235,9cyclictest181rcu_preempt12:15:061
11027998155,18cyclictest9259-21latency_hist11:30:542
11022998148,10cyclictest181rcu_preempt09:57:361
11018998162,14cyclictest13146-21latency_hist08:50:530
11018998143,7cyclictest181rcu_preempt10:35:110
11027998063,11cyclictest10582-21ssh12:26:242
11022998056,16cyclictest373-21lldpd10:01:131
11022998056,16cyclictest373-21lldpd10:01:131
11022998055,12cyclictest181rcu_preempt11:34:021
11022998055,12cyclictest181rcu_preempt11:34:021
11022998043,13cyclictest181rcu_preempt08:10:541
11022998043,13cyclictest181rcu_preempt08:10:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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