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2026-02-28 - 22:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Sat Feb 28, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236889911333,9cyclictest0-21swapper/009:56:290
23688991114,35cyclictest30722-21diskmemload09:21:280
236889910947,55cyclictest0-21swapper/009:31:140
236889910937,8cyclictest0-21swapper/008:11:490
23688991084,34cyclictest23672-21cyclictest07:06:160
23688991084,34cyclictest23672-21cyclictest07:06:160
23688991083,30cyclictest14628-21/usr/sbin/munin09:32:450
236889910750,49cyclictest0-21swapper/011:46:130
23734991063,56cyclictest14855-21apt-get12:16:272
237349910561,36cyclictest0-21swapper/209:36:142
236889910535,8cyclictest0-21swapper/011:11:480
236889910535,8cyclictest0-21swapper/011:11:480
236889910438,8cyclictest0-21swapper/012:06:140
236889910438,8cyclictest0-21swapper/012:06:140
23688991043,35cyclictest8264-21/usr/sbin/munin10:16:420
236889910418,28cyclictest7950-21kworker/u17:0+rpciod10:21:240
236889910418,28cyclictest7950-21kworker/u17:0+rpciod10:21:240
236889910342,10cyclictest31569-21kworker/u17:0+events_unbound07:11:110
236889910339,57cyclictest0-21swapper/012:21:280
236889910241,8cyclictest0-21swapper/010:50:330
236889910241,8cyclictest0-21swapper/010:50:330
23688991023,38cyclictest3245-21/usr/sbin/munin11:56:360
236889910133,8cyclictest0-21swapper/009:36:270
237349910046,47cyclictest1587-21sh09:11:292
23688991004,37cyclictest22761-21/usr/sbin/munin10:41:110
23688991004,37cyclictest22761-21/usr/sbin/munin10:41:110
236889910039,7cyclictest0-21swapper/012:31:430
236889910039,7cyclictest0-21swapper/012:31:430
236889910039,14cyclictest528-21threads10:56:480
236889910031,8cyclictest0-21swapper/009:11:400
23734999842,44cyclictest0-21swapper/209:21:292
2368899984,34cyclictest17484-21if_err_eth010:31:350
2368899983,36cyclictest22858-21latency_hist08:41:150
2368899983,36cyclictest22858-21latency_hist08:41:150
23688999815,32cyclictest4472-21rm11:03:580
2368899973,36cyclictest3720-21unixbench_multi10:07:460
2368899973,24cyclictest3497-21chrt07:41:330
2368899973,24cyclictest3497-21chrt07:41:330
23688999719,25cyclictest21295-21kworker/u17:2+rpciod09:46:470
23734999672,16cyclictest23672-21cyclictest09:46:452
23688999638,51cyclictest0-21swapper/008:01:110
23688999637,8cyclictest0-21swapper/012:11:280
23688999633,13cyclictest13224-21kworker/u19:1+events_unbound07:31:110
2368899962,28cyclictest19014-21grep08:26:450
23688999619,24cyclictest30219-21sed11:46:460
23688999619,24cyclictest30219-21sed11:46:460
23734999550,37cyclictest0-21swapper/210:38:552
23734999550,37cyclictest0-21swapper/210:38:552
23734999547,41cyclictest25045-21sh08:46:412
23734999538,49cyclictest0-21swapper/208:21:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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