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2026-04-04 - 22:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Sat Apr 04, 2026 12:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2673210714,59sleep02702-21apt-config07:03:540
200852940,7sleep10-21swapper/107:54:091
2941999356,28cyclictest8292-21sh08:58:522
2930999167,8cyclictest181rcu_preempt10:43:541
2930999053,11cyclictest181rcu_preempt07:44:261
2930999037,11cyclictest181rcu_preempt11:20:091
161429012,52sleep11651-21/usr/sbin/munin06:59:231
2930998667,11cyclictest7380-21kworker/u17:1-rpciod10:14:241
2930998657,10cyclictest11415-21ssh10:54:091
2941998570,9cyclictest28300-21modprobe09:33:512
2941998570,9cyclictest28300-21modprobe09:33:512
2941998570,8cyclictest0-21swapper/210:53:532
2930998562,16cyclictest2895-21cyclictest12:29:261
2941998450,17cyclictest28217-21kworker/u17:2-ext4-rsv-conversion11:43:532
179628414,44sleep30-21swapper/306:59:293
2941998363,10cyclictest0-21swapper/210:14:212
2941998356,8cyclictest181rcu_preempt07:29:142
2941998354,7cyclictest181rcu_preempt11:18:542
2941998349,7cyclictest181rcu_preempt08:33:552
2941998333,19cyclictest21683-21cpu07:59:092
2930998354,19cyclictest17433-21idleruntime10:09:151
2930998354,19cyclictest17433-21idleruntime10:09:151
2930998349,8cyclictest181rcu_preempt11:54:421
2918998353,10cyclictest58-21kcompactd007:43:540
2918998345,11cyclictest2895-21cyclictest10:37:460
2918998344,19cyclictest2895-21cyclictest11:59:590
2918998344,19cyclictest2895-21cyclictest11:59:590
2941998257,12cyclictest0-21swapper/211:58:532
2941998253,20cyclictest23548-21sort12:09:092
2941998250,10cyclictest181rcu_preempt07:54:262
2918998259,16cyclictest5058-21sh09:48:540
2918998244,10cyclictest181rcu_preempt09:15:230
2941998164,12cyclictest352-21runrttasks10:00:422
2941998152,12cyclictest181rcu_preempt07:38:552
2941998130,32cyclictest0-21swapper/212:02:542
2941998130,32cyclictest0-21swapper/212:02:542
2930998153,7cyclictest31-21ksoftirqd/111:06:411
2930998153,7cyclictest31-21ksoftirqd/111:06:411
2930998143,8cyclictest181rcu_preempt12:22:141
2930998142,11cyclictest181rcu_preempt11:50:041
2930998142,11cyclictest181rcu_preempt11:50:041
2930998142,11cyclictest181rcu_preempt11:50:041
2930998142,11cyclictest181rcu_preempt11:50:041
2930998132,11cyclictest181rcu_preempt10:59:241
2941998064,9cyclictest0-21swapper/210:28:542
2941998055,15cyclictest0-21swapper/210:09:132
2941998055,15cyclictest0-21swapper/210:09:132
2941998050,8cyclictest181rcu_preempt12:04:082
2941998035,18cyclictest58-21kcompactd008:39:252
2941998035,18cyclictest58-21kcompactd008:39:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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