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2026-01-10 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Sat Jan 10, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
459499986,40cyclictest15-21ksoftirqd/022:23:540
45242988,61sleep04522-21munin-run19:09:300
45242988,61sleep04522-21munin-run19:09:300
4614999756,13cyclictest181rcu_preempt19:24:512
4614999653,11cyclictest181rcu_preempt21:39:352
4614999458,11cyclictest181rcu_preempt22:16:282
4614999458,11cyclictest181rcu_preempt22:16:282
4614999453,10cyclictest181rcu_preempt20:34:312
4602999357,8cyclictest181rcu_preempt20:30:051
4614999255,9cyclictest181rcu_preempt23:51:032
4614999255,9cyclictest181rcu_preempt23:51:032
4614999255,7cyclictest181rcu_preempt23:14:472
41532926,15sleep20-21swapper/219:05:292
41532926,15sleep20-21swapper/219:05:292
4614999161,10cyclictest181rcu_preempt22:46:162
4614999056,8cyclictest181rcu_preempt21:05:042
36692907,59sleep13674-21ntpq19:05:031
36692907,59sleep13674-21ntpq19:05:031
4614998850,8cyclictest181rcu_preempt00:34:112
4614998845,18cyclictest0-21swapper/223:57:092
4614998845,18cyclictest0-21swapper/223:57:092
4602998859,11cyclictest181rcu_preempt00:11:481
4594998851,26cyclictest0-21swapper/023:24:300
4594998851,26cyclictest0-21swapper/023:24:300
4614998763,17cyclictest4585-21cyclictest21:10:022
4614998753,8cyclictest181rcu_preempt22:59:122
4614998750,11cyclictest181rcu_preempt19:20:032
4614998749,7cyclictest181rcu_preempt20:04:512
4602998760,19cyclictest18226-21sh22:12:201
4602998757,8cyclictest181rcu_preempt23:01:281
4602998757,8cyclictest181rcu_preempt23:01:281
4614998656,8cyclictest181rcu_preempt00:02:192
4614998652,8cyclictest181rcu_preempt20:54:502
4614998652,8cyclictest181rcu_preempt20:54:502
4614998651,8cyclictest181rcu_preempt23:00:142
4614998651,8cyclictest181rcu_preempt23:00:142
4614998650,9cyclictest181rcu_preempt00:15:472
4602998661,17cyclictest277-21dbus-daemon00:19:281
4602998653,10cyclictest181rcu_preempt23:53:471
4602998653,10cyclictest181rcu_preempt23:53:471
4602998648,8cyclictest181rcu_preempt22:28:591
460299862,38cyclictest31-21ksoftirqd/121:09:051
333828627,42sleep30-21swapper/319:04:533
333828627,42sleep30-21swapper/319:04:533
4614998558,8cyclictest181rcu_preempt23:39:542
4614998558,8cyclictest181rcu_preempt23:39:542
4614998551,9cyclictest181rcu_preempt00:26:402
4602998558,11cyclictest181rcu_preempt23:25:251
4602998554,8cyclictest181rcu_preempt21:59:511
4602998540,10cyclictest181rcu_preempt21:55:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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