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2026-06-26 - 15:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Jun 26, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4940215312,114sleep00-21swapper/006:54:260
4546210710,66sleep14030-21apt-get06:53:411
6035999648,9cyclictest181rcu_preempt09:38:412
45992967,58sleep24648-21/usr/sbin/munin06:54:112
6014999373,12cyclictest277-21dbus-daemon10:28:160
6025999157,15cyclictest181rcu_preempt09:06:481
6025999157,15cyclictest181rcu_preempt09:06:481
6025998838,8cyclictest0-21swapper/111:51:421
601499887,37cyclictest15-21ksoftirqd/011:41:040
6035998659,18cyclictest1353-21idleruntime-cro08:23:162
6035998659,18cyclictest1353-21idleruntime-cro08:23:162
6014998615,40cyclictest15-21ksoftirqd/011:03:170
6035998543,7cyclictest181rcu_preempt07:59:322
6035998543,11cyclictest181rcu_preempt07:33:432
6035998541,9cyclictest181rcu_preempt11:25:332
6025998549,10cyclictest181rcu_preempt09:34:011
6035998454,8cyclictest181rcu_preempt10:36:172
6035998454,13cyclictest181rcu_preempt10:53:422
6035998430,32cyclictest0-21swapper/208:23:422
6025998469,11cyclictest6004-21cyclictest07:58:391
6025998457,10cyclictest181rcu_preempt12:03:431
6025998438,12cyclictest23227-21proc_pri10:08:491
6025998438,12cyclictest23227-21proc_pri10:08:491
6035998361,16cyclictest2374-21systemd-journal11:19:422
6035998346,9cyclictest181rcu_preempt08:43:192
601499833,34cyclictest15-21ksoftirqd/009:58:180
6014998329,23cyclictest15-21ksoftirqd/011:11:040
6035998245,11cyclictest181rcu_preempt09:38:082
6035998237,13cyclictest181rcu_preempt11:36:442
6014998261,15cyclictest300-21rs:main0
6014998233,24cyclictest181rcu_preempt10:07:170
601499823,25cyclictest15-21ksoftirqd/010:13:280
601499822,52cyclictest19676-21snmpd10:58:190
6025998147,10cyclictest181rcu_preempt10:46:391
6035998051,12cyclictest181rcu_preempt07:53:412
6035998049,8cyclictest181rcu_preempt12:06:532
6035998049,8cyclictest181rcu_preempt07:43:442
6025998058,14cyclictest28131-21latency_hist09:23:201
6025998055,13cyclictest0-21swapper/107:58:181
6025998052,11cyclictest181rcu_preempt08:03:451
6025998041,11cyclictest181rcu_preempt08:43:341
6014998059,14cyclictest16712-21idleruntime-cro10:53:150
6035997953,19cyclictest20071-21sh09:09:272
6035997946,8cyclictest181rcu_preempt11:59:202
6035997944,9cyclictest181rcu_preempt10:40:342
6035997944,8cyclictest181rcu_preempt10:29:322
6035997944,8cyclictest181rcu_preempt10:29:322
6035997938,7cyclictest181rcu_preempt10:03:412
6035997931,12cyclictest181rcu_preempt07:28:332
6025997947,10cyclictest181rcu_preempt07:23:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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