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2026-02-17 - 08:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Tue Feb 17, 2026 00:44:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21035213113,82sleep121074-21cut19:02:241
224759912860,8cyclictest0-21swapper/000:12:000
224759912860,8cyclictest0-21swapper/000:12:000
224869912558,57cyclictest352-21runrttasks22:07:281
224869912558,57cyclictest352-21runrttasks22:07:281
224869911960,52cyclictest22456-21cyclictest22:47:351
224759911657,14cyclictest22456-21cyclictest21:21:590
22486991083,54cyclictest20877-21kworker/u19:1+ext4-rsv-conversion21:12:131
2614221010,7sleep30-21swapper/321:55:543
224869910138,10cyclictest0-21swapper/121:21:591
22492999943,10cyclictest181rcu_preempt19:12:332
22486999940,10cyclictest0-21swapper/121:52:141
22492999749,8cyclictest181rcu_preempt21:47:132
22486999540,13cyclictest12157-21latency_hist22:26:591
22486999534,15cyclictest0-21swapper/120:12:161
22486999534,15cyclictest0-21swapper/120:12:161
22486999534,13cyclictest0-21swapper/121:46:411
22486999333,13cyclictest0-21swapper/122:52:261
22475999371,12cyclictest0-21swapper/019:31:590
216632938,59sleep021753-21cat19:02:440
22486999239,8cyclictest0-21swapper/123:57:001
22486999231,15cyclictest0-21swapper/119:32:271
22475999169,12cyclictest0-21swapper/020:31:590
22486999034,18cyclictest6232-21latency_hist22:16:591
22475999068,12cyclictest0-21swapper/020:26:590
22475999068,11cyclictest0-21swapper/020:17:000
22475999068,11cyclictest0-21swapper/020:17:000
22475998969,9cyclictest0-21swapper/021:02:220
2107728911,53sleep221132-21/usr/sbin/munin19:02:252
22475998868,9cyclictest0-21swapper/020:01:590
22475998838,8cyclictest181rcu_preempt22:15:420
22486998736,12cyclictest23924-21unixbench_multi20:47:341
22475998771,8cyclictest0-21swapper/000:22:230
22475998771,8cyclictest0-21swapper/000:22:230
22486998632,9cyclictest0-21swapper/120:57:131
22486998632,9cyclictest0-21swapper/120:57:131
22475998667,9cyclictest0-21swapper/019:47:150
22492998566,9cyclictest0-21swapper/222:02:132
2248699852,30cyclictest17349-21/usr/sbin/munin20:27:331
22486998513,29cyclictest12165-21latency_hist00:16:591
22475998569,8cyclictest0-21swapper/021:52:350
22475998553,7cyclictest181rcu_preempt20:32:210
22475998467,11cyclictest277-21dbus-daemon22:56:580
22475998465,7cyclictest0-21swapper/020:51:590
22475998462,17cyclictest22456-21cyclictest00:32:070
22475998462,17cyclictest22456-21cyclictest00:32:070
22492998344,8cyclictest181rcu_preempt23:47:112
22475998366,8cyclictest0-21swapper/019:11:590
22486998229,9cyclictest0-21swapper/120:07:301
22492998135,8cyclictest181rcu_preempt19:52:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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