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2026-02-27 - 19:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Feb 27, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156252990,6sleep20-21swapper/209:56:402
156252990,6sleep20-21swapper/209:56:402
10013999973,17cyclictest14651-21ntp_kernel_pll_08:56:442
10004999455,16cyclictest181rcu_preempt12:12:410
10013999355,13cyclictest181rcu_preempt10:58:542
10013999165,17cyclictest29444-21timerandwakeup12:06:502
10013998963,17cyclictest298-21in:imuxsock08:26:152
10013998963,17cyclictest298-21in:imuxsock08:26:152
10013998853,11cyclictest181rcu_preempt11:41:372
10013998853,11cyclictest181rcu_preempt11:41:372
10013998849,18cyclictest4538-21fschecks_count10:32:442
10013998844,17cyclictest181rcu_preempt12:06:132
10013998825,19cyclictest0-21swapper/209:07:452
10013998825,19cyclictest0-21swapper/209:07:452
10004998845,13cyclictest181rcu_preempt11:21:510
10004998763,15cyclictest31210-21unixbench_singl10:21:530
10004998763,15cyclictest31210-21unixbench_singl10:21:530
10013998649,11cyclictest181rcu_preempt11:56:462
10004998651,9cyclictest181rcu_preempt07:46:350
10004998651,9cyclictest181rcu_preempt07:46:350
10004998645,8cyclictest181rcu_preempt07:51:270
10004998645,8cyclictest181rcu_preempt07:51:270
10004998643,13cyclictest181rcu_preempt08:01:440
914728516,35sleep10-21swapper/107:01:571
914728516,35sleep10-21swapper/107:01:571
1000499855,33cyclictest15-21ksoftirqd/008:31:300
10004998550,16cyclictest300-21rs:main0
10013998467,9cyclictest0-21swapper/210:26:172
10013998467,9cyclictest0-21swapper/210:26:172
10013998463,15cyclictest962-21latency_hist08:16:182
10013998463,15cyclictest962-21latency_hist08:16:182
10013998444,10cyclictest181rcu_preempt12:26:562
10004998468,10cyclictest23097-21cron09:16:150
1000499844,37cyclictest24114-21/usr/sbin/munin09:16:480
10013998365,12cyclictest6813-21ssh09:41:472
10013998361,13cyclictest32653-21ssh11:18:102
10013998358,15cyclictest12692-21latency_hist10:46:172
10013998355,20cyclictest544-21cron11:36:152
10013998353,13cyclictest181rcu_preempt07:26:422
10013998333,26cyclictest9993-21cyclictest08:06:372
10013998328,23cyclictest0-21swapper/211:11:422
10013998328,23cyclictest0-21swapper/211:11:422
10004998354,12cyclictest181rcu_preempt08:11:380
10004998354,12cyclictest181rcu_preempt08:11:380
10013998250,12cyclictest181rcu_preempt11:26:342
10013998250,12cyclictest181rcu_preempt11:26:342
10013998246,26cyclictest30404-21latency_hist08:06:192
10013998234,27cyclictest0-21swapper/207:57:132
10009998267,9cyclictest4234-21latency_hist08:26:171
10009998267,9cyclictest4234-21latency_hist08:26:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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