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2026-06-06 - 01:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Jun 05, 2026 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13797218413,123sleep11-21systemd06:59:451
13896999978,14cyclictest352-21runrttasks12:25:042
13883999466,19cyclictest20790-21diskmemload09:11:530
13883999466,19cyclictest20790-21diskmemload09:11:530
13896999269,15cyclictest0-21swapper/208:19:442
13896999269,15cyclictest0-21swapper/208:19:442
13896999249,12cyclictest23759-21ssh09:57:542
13896999050,10cyclictest181rcu_preempt09:40:172
13883999054,11cyclictest181rcu_preempt12:08:060
13883999054,11cyclictest181rcu_preempt12:08:060
128782909,55sleep012402-21/usr/sbin/munin06:55:150
13891998970,13cyclictest17016-21sh11:35:011
13883998866,14cyclictest5261-21fschecks_time11:15:030
13896998665,14cyclictest7116-21idleruntime-cro10:24:422
13896998665,14cyclictest7116-21idleruntime-cro10:24:422
13896998651,13cyclictest6364-21ssh12:10:432
13896998642,12cyclictest181rcu_preempt07:49:542
13891998664,16cyclictest9779-21fschecks_count09:35:031
13891998664,16cyclictest9779-21fschecks_count09:35:031
13896998554,8cyclictest5721-21ssh09:28:162
13883998558,18cyclictest3442-21latency08:05:070
13883998558,18cyclictest3442-21latency08:05:070
1263928512,42sleep212689-21cut06:55:092
1389699846,65cyclictest13785-21kworker/u19:0+ext4-rsv-conversion08:45:062
13891998465,13cyclictest8268-21sh10:26:091
13883998463,14cyclictest13587-21sh11:29:430
13883998456,19cyclictest1119-21latency_hist10:14:450
1389199837,41cyclictest31-21ksoftirqd/111:19:351
13883998362,12cyclictest0-21swapper/011:06:090
13883998362,12cyclictest0-21swapper/011:06:090
13883998356,9cyclictest181rcu_preempt10:26:020
13883998350,12cyclictest181rcu_preempt07:44:450
13883998330,26cyclictest0-21swapper/009:14:580
1389199829,36cyclictest31-21ksoftirqd/107:23:391
13891998260,16cyclictest487-21sh11:06:201
13891998260,16cyclictest487-21sh11:06:201
13891998210,36cyclictest31-21ksoftirqd/111:04:401
13891998210,36cyclictest31-21ksoftirqd/111:04:401
13883998254,9cyclictest181rcu_preempt10:39:460
13883998247,12cyclictest181rcu_preempt11:50:030
13883998243,19cyclictest181rcu_preempt11:48:370
630828110,61sleep06313-21ssh09:29:440
13896998166,8cyclictest0-21swapper/211:24:532
13896998159,12cyclictest0-21swapper/211:10:012
13896998153,19cyclictest21723-21threads07:20:162
13896998147,13cyclictest21448-21ssh10:48:022
13883998151,11cyclictest181rcu_preempt09:35:030
13883998151,11cyclictest181rcu_preempt09:35:030
13883998120,40cyclictest0-21swapper/008:10:040
13883998120,40cyclictest0-21swapper/008:10:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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