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2026-03-30 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Mon Mar 30, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13767991192,86cyclictest29109-21apt-get19:49:262
13767991192,86cyclictest29109-21apt-get19:49:262
13767991182,83cyclictest28958-21dpkg23:05:112
137629911550,33cyclictest28841-21ssh22:09:551
137629910351,42cyclictest803-21sendmail-mta00:11:201
1331121036,17sleep10-21swapper/119:00:261
1942221000,6sleep219398-21ssh21:54:462
13767999970,20cyclictest12001-21sh00:24:492
13762999726,36cyclictest21049-21sh22:50:391
13767999646,13cyclictest0-21swapper/222:04:552
1376299952,81cyclictest0-21swapper/121:39:281
13767999459,14cyclictest181rcu_preempt22:28:452
13767999445,14cyclictest0-21swapper/221:47:032
13767999351,11cyclictest181rcu_preempt19:44:432
13767999344,15cyclictest0-21swapper/223:30:232
13767999340,38cyclictest0-21swapper/221:53:232
13767999312,51cyclictest39-21ksoftirqd/220:13:132
13767999312,51cyclictest39-21ksoftirqd/220:13:132
13762999249,37cyclictest352-21runrttasks21:53:491
13767999160,22cyclictest30952-21fschecks_count19:54:362
13767999156,8cyclictest181rcu_preempt21:10:492
13767999053,13cyclictest181rcu_preempt20:54:162
13762999026,31cyclictest0-21swapper/123:12:081
13762999026,31cyclictest0-21swapper/123:12:081
13762999021,38cyclictest0-21swapper/122:42:231
13762999021,38cyclictest0-21swapper/122:42:231
13767998964,18cyclictest13745-21cyclictest23:14:512
13767998950,17cyclictest181rcu_preempt00:01:272
13767998950,17cyclictest181rcu_preempt00:01:272
13767998936,37cyclictest0-21swapper/219:19:522
13762998967,15cyclictest23591-21sh22:54:481
13767998860,18cyclictest27076-21latency_hist19:44:162
13767998851,17cyclictest181rcu_preempt23:20:152
13767998851,17cyclictest181rcu_preempt23:20:152
13767998844,9cyclictest0-21swapper/222:13:222
13767998843,12cyclictest181rcu_preempt00:05:052
13762998846,34cyclictest0-21swapper/123:59:251
13762998846,34cyclictest0-21swapper/123:59:251
13762998844,36cyclictest0-21swapper/121:44:481
13767998755,8cyclictest181rcu_preempt23:39:302
13767998753,8cyclictest181rcu_preempt20:54:522
13767998748,14cyclictest181rcu_preempt19:09:392
13767998748,14cyclictest181rcu_preempt19:09:392
13762998745,34cyclictest0-21swapper/121:15:461
13762998742,35cyclictest1240-21modprobe20:04:141
13762998726,27cyclictest0-21swapper/122:19:371
13767998650,8cyclictest181rcu_preempt23:44:472
13767998638,13cyclictest0-21swapper/222:55:422
13767998637,12cyclictest181rcu_preempt22:30:012
13767998629,18cyclictest0-21swapper/222:50:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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