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2026-05-20 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Wed May 20, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
581421127,16sleep00-21swapper/018:57:240
62319910452,22cyclictest6216-21cyclictest21:29:221
62369910258,13cyclictest181rcu_preempt00:26:092
62319910120,39cyclictest31-21ksoftirqd/122:26:171
62269910014,56cyclictest14153-21ssh22:49:330
6236999766,8cyclictest181rcu_preempt22:43:352
6236999663,9cyclictest181rcu_preempt19:55:512
6231999559,11cyclictest181rcu_preempt22:50:161
6231999460,8cyclictest181rcu_preempt19:01:241
6236999361,12cyclictest181rcu_preempt23:01:552
6236999361,12cyclictest181rcu_preempt23:01:552
176752930,7sleep20-21swapper/223:49:292
176752930,7sleep20-21swapper/223:49:292
6236999175,10cyclictest20168-21kworker/u17:2-rpciod00:21:162
6236999175,10cyclictest20168-21kworker/u17:2-rpciod00:21:162
6236999050,15cyclictest181rcu_preempt20:05:532
623699902,50cyclictest39-21ksoftirqd/223:20:522
6231999059,9cyclictest181rcu_preempt23:09:241
6231999051,11cyclictest181rcu_preempt20:11:371
622699909,28cyclictest12546-21apt23:40:590
6226999024,29cyclictest0-21swapper/023:28:500
6236998940,16cyclictest181rcu_preempt20:26:482
6236998940,16cyclictest181rcu_preempt20:26:482
6231998969,14cyclictest0-21swapper/119:21:221
623199896,49cyclictest31-21ksoftirqd/121:46:051
623199896,49cyclictest31-21ksoftirqd/121:46:051
6226998821,39cyclictest0-21swapper/021:11:240
6236998762,8cyclictest181rcu_preempt00:15:132
6236998741,13cyclictest181rcu_preempt21:16:072
6231998750,9cyclictest181rcu_preempt21:15:351
6231998734,24cyclictest58-21kcompactd023:56:001
6231998734,24cyclictest58-21kcompactd023:56:001
6231998666,7cyclictest181rcu_preempt22:31:581
6231998663,12cyclictest0-21swapper/122:21:101
6231998652,7cyclictest181rcu_preempt19:50:531
6231998645,10cyclictest6216-21cyclictest19:12:461
6231998644,9cyclictest0-21swapper/119:56:071
6236998559,9cyclictest181rcu_preempt22:06:292
623699853,65cyclictest3067-21apt-get22:31:152
6231998563,16cyclictest12795-21sh23:41:111
6226998570,10cyclictest9778-21cron19:10:490
6236998453,8cyclictest181rcu_preempt19:19:142
6236998450,9cyclictest181rcu_preempt22:11:122
6236998448,10cyclictest181rcu_preempt22:16:122
623699843,44cyclictest29930-21apt-get20:11:162
6231998457,13cyclictest181rcu_preempt21:01:061
6231998457,13cyclictest181rcu_preempt21:01:061
6231998451,14cyclictest181rcu_preempt20:16:221
6236998353,11cyclictest181rcu_preempt20:07:492
6236998351,7cyclictest181rcu_preempt23:26:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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