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2026-09-05 - 02:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Sep 04, 2026 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26799910372,22cyclictest25364-21fschecks_time10:25:160
836021020,5sleep18359-21fschecks_count07:25:161
2689999982,11cyclictest12202-21ssh10:04:572
2689999982,11cyclictest12202-21ssh10:04:572
167632980,7sleep30-21swapper/307:50:263
2679999372,14cyclictest2670-21cyclictest10:34:260
2679999059,20cyclictest19345-21latency_hist07:59:580
2679999059,20cyclictest19345-21latency_hist07:59:580
2689998968,14cyclictest2670-21cyclictest10:59:582
2679998960,22cyclictest13553-21sh10:05:300
2679998943,9cyclictest181rcu_preempt11:24:050
253428915,48sleep12537-21cron07:09:541
2679998761,19cyclictest0-21swapper/012:30:260
2689998642,16cyclictest0-21swapper/212:37:122
2684998545,15cyclictest32716-21cstates09:46:071
2689998467,11cyclictest200-21systemd-journal10:07:262
2679998463,11cyclictest0-21swapper/011:05:290
24252847,54sleep20-21swapper/207:08:292
2689998353,21cyclictest12856-21latency_hist09:14:572
2679998260,16cyclictest15321-21sh11:00:220
2689998151,9cyclictest181rcu_preempt11:46:572
2689998137,20cyclictest23149-21ssh10:20:462
2679998159,16cyclictest20442-21unixbench_singl09:25:310
2679998159,16cyclictest20442-21unixbench_singl09:25:310
2679998152,9cyclictest181rcu_preempt11:30:260
2679998152,19cyclictest3005-21timerandwakeup10:40:300
2689998055,8cyclictest181rcu_preempt09:39:312
2689998055,8cyclictest181rcu_preempt09:39:312
2689998047,9cyclictest181rcu_preempt11:35:352
2689998038,9cyclictest181rcu_preempt11:27:542
2684998064,11cyclictest2670-21cyclictest12:15:281
167228017,39sleep00-21swapper/007:05:290
2689997953,8cyclictest181rcu_preempt11:12:082
2689997953,8cyclictest181rcu_preempt11:12:082
2689997948,8cyclictest181rcu_preempt07:32:372
2689997948,8cyclictest181rcu_preempt07:32:372
2689997947,8cyclictest181rcu_preempt10:15:362
2689997947,10cyclictest181rcu_preempt09:00:162
2689997846,7cyclictest181rcu_preempt07:39:092
2689997836,10cyclictest28810-21ssh11:21:282
2679997858,12cyclictest0-21swapper/009:59:580
2679997858,11cyclictest0-21swapper/012:29:530
2679997855,16cyclictest22566-21latency_hist08:09:580
2679997839,28cyclictest0-21swapper/010:04:540
2679997839,28cyclictest0-21swapper/010:04:540
2689997752,18cyclictest524-21in:imuxsock07:59:262
2689997752,18cyclictest524-21in:imuxsock07:59:262
2689997736,17cyclictest20522-21ssh11:09:332
2689997734,20cyclictest32760-21ssh10:36:142
2689997733,17cyclictest0-21swapper/207:45:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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