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2026-06-07 - 02:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Sat Jun 06, 2026 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28850213516,32sleep30-21swapper/318:59:403
290289910263,18cyclictest181rcu_preempt23:05:152
290289910263,18cyclictest181rcu_preempt23:05:152
29023999857,15cyclictest181rcu_preempt23:14:401
29023999854,12cyclictest181rcu_preempt19:06:241
29023999854,12cyclictest181rcu_preempt19:06:241
29023999854,11cyclictest181rcu_preempt23:29:441
29023999854,11cyclictest181rcu_preempt23:29:441
288142986,16sleep20-21swapper/218:59:102
29023999748,14cyclictest10814-21kworker/u19:3-flush-0:3222:22:451
29019999636,32cyclictest0-21swapper/021:35:140
29028999369,8cyclictest181rcu_preempt19:10:122
29028999369,8cyclictest181rcu_preempt19:10:122
29028999360,10cyclictest181rcu_preempt22:26:342
29028999360,10cyclictest181rcu_preempt22:26:342
29028999348,10cyclictest181rcu_preempt00:20:052
29028999348,10cyclictest181rcu_preempt00:20:052
2759429324,36sleep00-21swapper/018:55:000
29023999262,9cyclictest181rcu_preempt22:25:241
29023999262,9cyclictest181rcu_preempt22:25:241
29023999244,12cyclictest181rcu_preempt21:03:241
29023999235,19cyclictest0-21swapper/100:29:421
29019999270,12cyclictest20957-21sshd23:15:230
29019999270,12cyclictest20957-21sshd23:15:230
29028999148,16cyclictest181rcu_preempt19:55:152
29028999148,16cyclictest181rcu_preempt19:55:152
29023999161,11cyclictest181rcu_preempt23:44:581
29023999161,11cyclictest181rcu_preempt23:44:581
2902899904,50cyclictest39-21ksoftirqd/223:50:182
29023999050,8cyclictest181rcu_preempt21:35:591
29023998954,13cyclictest181rcu_preempt23:00:131
29028998858,8cyclictest181rcu_preempt23:18:012
29028998858,8cyclictest181rcu_preempt23:18:012
29028998849,8cyclictest181rcu_preempt22:58:522
29028998847,10cyclictest181rcu_preempt22:33:482
29028998842,13cyclictest181rcu_preempt23:40:232
29028998842,13cyclictest181rcu_preempt23:40:232
29028998829,26cyclictest0-21swapper/220:45:162
29023998875,9cyclictest29011-21cyclictest21:45:151
29023998875,9cyclictest29011-21cyclictest21:45:151
29023998852,14cyclictest181rcu_preempt22:40:051
29023998845,8cyclictest181rcu_preempt21:22:591
29023998838,18cyclictest0-21swapper/100:17:501
29028998768,12cyclictest9656-21kworker/u17:2-rpciod22:16:402
29028998756,12cyclictest181rcu_preempt21:59:462
29028998734,18cyclictest0-21swapper/221:12:022
29028998734,18cyclictest0-21swapper/221:12:022
29028998732,35cyclictest0-21swapper/223:47:532
29028998732,35cyclictest0-21swapper/223:47:532
29028998731,17cyclictest0-21swapper/220:00:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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