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2026-02-14 - 19:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Sat Feb 14, 2026 12:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1578321169,77sleep115850-21latency07:02:391
169229911059,45cyclictest23949-21threads09:03:162
1288421060,5sleep30-21swapper/309:40:213
169229910255,40cyclictest5680-21/usr/sbin/munin12:12:222
169229910237,34cyclictest0-21swapper/210:27:212
16922991003,63cyclictest22781-21ssh09:57:222
169229910031,37cyclictest0-21swapper/208:54:072
16903999970,20cyclictest19984-21fschecks_count09:52:280
16903999970,20cyclictest19984-21fschecks_count09:52:280
116202980,6sleep00-21swapper/011:27:250
16914999664,9cyclictest181rcu_preempt09:48:241
16903999610,43cyclictest15-21ksoftirqd/011:42:440
16922999535,50cyclictest0-21swapper/212:02:282
16922999425,37cyclictest0-21swapper/209:34:012
16914999458,13cyclictest181rcu_preempt09:26:101
1690399946,46cyclictest15-21ksoftirqd/008:39:260
16914999362,10cyclictest181rcu_preempt09:39:271
16914999344,8cyclictest181rcu_preempt11:02:351
16922999240,40cyclictest20797-21sh09:52:452
16922999240,40cyclictest20797-21sh09:52:452
16914999269,15cyclictest2826-21systemd-run08:02:081
1552029240,32sleep215532-21cstates07:02:282
16914999157,13cyclictest181rcu_preempt11:17:251
16922999071,14cyclictest16890-21cyclictest07:07:442
16922999071,14cyclictest16890-21cyclictest07:07:442
16914999066,15cyclictest15863-21ssh11:33:441
16922998923,41cyclictest0-21swapper/211:54:052
16922998916,39cyclictest24493-21diskmemload10:16:232
16914998946,12cyclictest181rcu_preempt07:17:221
16903998959,21cyclictest27024-21latency_hist07:37:100
16903998943,11cyclictest181rcu_preempt12:31:420
16922998843,39cyclictest18792-21uptime07:12:142
16914998860,15cyclictest181rcu_preempt07:52:341
16914998860,15cyclictest181rcu_preempt07:52:341
16914998842,9cyclictest181rcu_preempt08:58:371
16903998824,35cyclictest15-21ksoftirqd/009:45:510
16922998764,16cyclictest16464-21cron09:47:072
16922998744,35cyclictest0-21swapper/212:22:302
16914998732,17cyclictest181rcu_preempt10:31:391
16903998728,32cyclictest15-21ksoftirqd/012:02:090
165452877,17sleep00-21swapper/007:04:260
1692299865,53cyclictest0-21swapper/210:45:332
1692299865,53cyclictest0-21swapper/210:45:332
1692299862,71cyclictest11099-21ssh10:32:232
16914998662,14cyclictest0-21swapper/108:22:101
16914998628,28cyclictest0-21swapper/108:12:591
16914998628,28cyclictest0-21swapper/108:12:591
16903998666,10cyclictest0-21swapper/008:02:290
16922998565,13cyclictest14273-21fschecks_count10:37:282
1692299854,73cyclictest0-21swapper/207:52:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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