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2026-09-04 - 03:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Fri Sep 04, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24569215811,105sleep024638-21fschecks_time19:05:240
2540821056,16sleep10-21swapper/119:05:541
25865999462,8cyclictest181rcu_preempt22:15:002
25865999451,17cyclictest18082-21ssh22:27:442
25865999451,17cyclictest18082-21ssh22:27:442
25862999348,13cyclictest15123-21ssh23:14:291
25865999063,8cyclictest181rcu_preempt19:50:332
25862999063,10cyclictest181rcu_preempt23:39:371
25856998917,41cyclictest15-21ksoftirqd/022:50:160
25865998865,12cyclictest0-21swapper/223:14:592
25865998763,14cyclictest0-21swapper/220:00:192
25865998763,14cyclictest0-21swapper/220:00:192
25865998666,10cyclictest0-21swapper/220:45:192
25865998662,12cyclictest0-21swapper/220:25:002
25865998662,12cyclictest0-21swapper/220:25:002
25865998643,13cyclictest359-21snmpd00:23:022
25865998638,9cyclictest181rcu_preempt22:30:082
25865998638,9cyclictest181rcu_preempt22:30:082
25862998553,11cyclictest181rcu_preempt19:15:411
25862998553,11cyclictest181rcu_preempt19:15:411
2585699854,41cyclictest15-21ksoftirqd/019:55:340
25865998464,11cyclictest0-21swapper/223:30:002
25865998444,10cyclictest58-21kcompactd019:45:162
25856998448,10cyclictest181rcu_preempt19:15:260
25856998448,10cyclictest181rcu_preempt19:15:260
25856998447,10cyclictest58-21kcompactd020:35:310
25865998344,9cyclictest181rcu_preempt23:42:132
25862998356,11cyclictest181rcu_preempt22:52:331
25862998344,13cyclictest181rcu_preempt21:28:141
25862998246,14cyclictest31-21ksoftirqd/123:17:291
25865998162,9cyclictest0-21swapper/220:15:332
25865998162,10cyclictest0-21swapper/220:55:182
25865998161,12cyclictest0-21swapper/220:35:192
25856998140,10cyclictest181rcu_preempt21:58:460
25865998042,17cyclictest7682-21if_eth021:20:232
25865997963,9cyclictest0-21swapper/220:05:142
25865997948,7cyclictest181rcu_preempt23:07:392
25865997938,16cyclictest381ktimers/200:15:342
25862997948,8cyclictest181rcu_preempt19:45:091
25856997917,8cyclictest181rcu_preempt22:20:310
25865997861,8cyclictest0-21swapper/219:40:002
25865997861,8cyclictest0-21swapper/219:40:002
25865997856,16cyclictest11469-40mandb00:00:542
25865997856,16cyclictest11469-40mandb00:00:542
25865997846,15cyclictest29190-21kworker/u18:1-events_unbound22:24:072
25862997856,14cyclictest0-21swapper/120:00:331
25862997856,14cyclictest0-21swapper/120:00:331
25862997841,7cyclictest181rcu_preempt21:05:001
25862997841,7cyclictest181rcu_preempt21:05:001
25856997860,12cyclictest524-21in:imuxsock20:04:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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