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2026-07-16 - 12:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Thu Jul 16, 2026 00:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7713214411,93sleep27788-21cstates18:52:172
8756211911,87sleep00-21swapper/018:53:340
1554621070,7sleep10-21swapper/123:36:281
2715421050,7sleep10-21swapper/121:13:081
91809910459,8cyclictest181rcu_preempt20:36:582
9169999714,32cyclictest25164-21/usr/sbin/munin22:57:330
9173999560,9cyclictest181rcu_preempt00:11:581
9173999560,9cyclictest181rcu_preempt00:11:581
917399953,72cyclictest4373-21ssh23:18:011
917399953,72cyclictest4373-21ssh23:18:011
9173999425,19cyclictest0-21swapper/121:29:081
9180999370,15cyclictest170-21jbd2/mmcblk2p2-821:07:002
9180999237,17cyclictest0-21swapper/219:50:132
9173999147,12cyclictest181rcu_preempt22:18:311
85872917,54sleep18671-21sed18:52:451
9180998959,8cyclictest181rcu_preempt21:20:252
9180998947,16cyclictest181rcu_preempt22:18:162
9180998913,50cyclictest39-21ksoftirqd/222:57:292
9173998953,13cyclictest181rcu_preempt21:33:461
9173998953,13cyclictest181rcu_preempt21:33:461
9173998937,33cyclictest0-21swapper/123:51:461
9180998874,10cyclictest9156-21cyclictest19:11:582
9180998860,7cyclictest181rcu_preempt22:01:342
9173998854,7cyclictest181rcu_preempt21:02:211
9173998837,28cyclictest0-21swapper/122:06:491
9173998758,21cyclictest1-21systemd21:54:071
9173998758,21cyclictest1-21systemd21:54:071
9173998738,26cyclictest0-21swapper/123:24:301
9173998730,28cyclictest9156-21cyclictest22:13:161
9173998730,28cyclictest9156-21cyclictest22:13:161
9173998665,16cyclictest9156-21cyclictest19:39:071
9173998655,8cyclictest181rcu_preempt21:59:021
916999864,31cyclictest0-21swapper/021:16:560
9180998537,27cyclictest0-21swapper/219:17:312
9180998537,27cyclictest0-21swapper/219:17:312
9173998551,11cyclictest181rcu_preempt22:27:281
9173998547,15cyclictest181rcu_preempt22:22:011
9173998547,15cyclictest181rcu_preempt22:22:011
9180998452,12cyclictest181rcu_preempt21:30:072
9180998450,13cyclictest181rcu_preempt22:06:032
9180998412,46cyclictest39-21ksoftirqd/220:47:272
9173998459,8cyclictest181rcu_preempt20:02:311
9173998438,22cyclictest9156-21cyclictest23:55:011
9173998438,22cyclictest9156-21cyclictest23:55:011
9169998449,29cyclictest31350-21fschecks_time00:02:170
9169998449,29cyclictest31350-21fschecks_time00:02:170
9180998351,9cyclictest181rcu_preempt20:27:072
9180998329,11cyclictest0-21swapper/221:39:132
9173998355,8cyclictest181rcu_preempt21:09:341
9173998355,8cyclictest181rcu_preempt00:22:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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