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2025-12-03 - 20:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot7.osadl.org (updated Wed Dec 03, 2025 12:44:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1451721309,91sleep10-21swapper/107:04:201
15402991097,62cyclictest14210-21apt-get11:53:511
154109910753,19cyclictest314-21in:imuxsock10:43:382
14501210711,70sleep014516-21/usr/sbin/munin07:04:190
15402999648,12cyclictest181rcu_preempt10:04:081
1541099943,82cyclictest31354-21sed11:24:152
15402999444,15cyclictest0-21swapper/107:23:531
1541099903,68cyclictest31891-21apt-get07:59:032
1539899902,47cyclictest15-21ksoftirqd/008:20:250
15402998950,9cyclictest181rcu_preempt10:42:581
15402998950,8cyclictest181rcu_preempt08:28:531
15402998950,8cyclictest181rcu_preempt08:28:531
1539899892,54cyclictest15-21ksoftirqd/008:54:060
1534228912,47sleep239-21ksoftirqd/207:08:412
1540299882,61cyclictest355-21runrttasks10:09:301
15402998754,9cyclictest181rcu_preempt11:16:081
15402998656,12cyclictest181rcu_preempt09:33:571
15398998645,8cyclictest181rcu_preempt11:20:080
15410998569,10cyclictest27317-21/usr/sbin/munin12:19:172
15410998554,22cyclictest19300-21modprobe10:03:372
15410998554,22cyclictest19300-21modprobe10:03:372
15402998540,12cyclictest181rcu_preempt12:34:201
15398998524,50cyclictest13662-21apt-get11:53:520
1541099843,59cyclictest5036-21apt-get08:13:562
15402998457,19cyclictest22874-21latency07:29:041
15402998441,16cyclictest181rcu_preempt11:30:301
15402998441,16cyclictest181rcu_preempt11:30:301
15398998417,54cyclictest31137-21/usr/sbin/munin11:24:120
1541099835,54cyclictest22407-21apt-get10:08:542
1539899833,48cyclictest15-21ksoftirqd/010:04:080
15410998267,10cyclictest15389-21cyclictest11:38:392
15410998238,35cyclictest7541-21grep08:19:162
15402998255,18cyclictest22803-21diskmemload09:11:541
15402998254,18cyclictest31080-21latency_hist09:23:411
15402998247,12cyclictest181rcu_preempt12:03:521
15402998243,9cyclictest181rcu_preempt11:23:371
15402998238,20cyclictest181rcu_preempt09:54:031
15402998233,12cyclictest181rcu_preempt10:24:121
1539899823,47cyclictest15-21ksoftirqd/010:39:000
15410998122,25cyclictest17732-21sh10:59:152
15410998121,28cyclictest0-21swapper/210:34:042
15402998155,10cyclictest181rcu_preempt11:48:531
15402998149,13cyclictest181rcu_preempt10:18:411
15402998149,13cyclictest181rcu_preempt10:18:411
15398998136,12cyclictest181rcu_preempt08:32:250
15398998136,12cyclictest181rcu_preempt08:32:250
15402998057,16cyclictest0-21swapper/111:24:081
15402998044,13cyclictest181rcu_preempt11:34:391
15398998046,23cyclictest12536-21cat08:34:130
15410997963,11cyclictest22803-21diskmemload11:55:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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