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2026-02-02 - 22:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot8.osadl.org (updated Mon Feb 02, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587502395810irq/54-eth00-21swapper/107:06:461
1143527860sleep00-21swapper/007:06:530
11947997318cyclictest28297-21threads11:20:251
11947997318cyclictest20151-21vmstat12:35:251
11947997318cyclictest14565-21ntp_states08:55:201
11947997217cyclictest30353-21munin-node1
11947997217cyclictest30353-21munin-node1
11947997217cyclictest23876-21df_inode09:25:141
11947997217cyclictest17615-21diskstats07:25:141
11947997217cyclictest1584-21grep08:15:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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