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2026-01-24 - 12:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Sat Jan 24, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587506759070irq/54-eth00-21swapper/119:09:041
8799998126cyclictest0-21swapper/021:25:140
866127860sleep00-21swapper/019:09:210
8799997318cyclictest0-21swapper/022:45:150
8799997236cyclictest0-21swapper/023:55:150
8799997217cyclictest0-21swapper/019:30:140
8799996914cyclictest0-21swapper/023:00:250
8799996914cyclictest0-21swapper/020:40:140
8799996712cyclictest0-21swapper/022:15:140
8799996529cyclictest0-21swapper/000:25:160
879999649cyclictest0-21swapper/000:39:400
879999649cyclictest0-21swapper/000:39:400
8799996428cyclictest0-21swapper/021:10:150
879999638cyclictest0-21swapper/020:00:140
8799996327cyclictest0-21swapper/019:23:310
8799996327cyclictest0-21swapper/000:10:130
8799996125cyclictest0-21swapper/021:32:490
8799996125cyclictest0-21swapper/000:20:130
8805996024cyclictest755-21munin-node1
8805996024cyclictest0-21swapper/123:13:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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