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2026-07-21 - 02:42

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot8s (updated Mon Jul 20, 2026 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7428892150136,9sleep50-21swapper/507:09:205
742855212191,10sleep00-21swapper/007:08:510
7428302121107,9sleep20-21swapper/207:08:292
7427222116101,10sleep60-21swapper/607:06:566
742692211499,10sleep30-21swapper/307:06:283
742740211399,9sleep40-21swapper/407:07:104
742663211399,9sleep10-21swapper/107:06:031
740866211096,9sleep70-21swapper/707:05:137
7432009910299,3cyclictest553-21snmpd08:23:196
7431929910299,3cyclictest553-21snmpd11:20:434
7431929910299,2cyclictest553-21snmpd11:00:184
743192991020,102cyclictest0-21swapper/410:57:214
743203991010,99cyclictest0-21swapper/708:17:437
743203991010,100cyclictest0-21swapper/712:13:187
743196991010,99cyclictest0-21swapper/509:27:065
743196991010,100cyclictest0-21swapper/507:27:565
743196991010,100cyclictest0-21swapper/507:27:565
7431929910199,2cyclictest553-21snmpd12:34:194
7431929910199,2cyclictest553-21snmpd10:26:354
7431929910199,2cyclictest553-21snmpd10:18:054
7431929910199,2cyclictest553-21snmpd09:38:134
7431929910199,2cyclictest553-21snmpd08:53:414
743192991010,101cyclictest0-21swapper/410:40:214
743192991010,101cyclictest0-21swapper/407:18:534
743192991010,100cyclictest0-21swapper/408:33:474
743192991010,100cyclictest0-21swapper/407:28:384
743192991010,100cyclictest0-21swapper/407:28:384
7431879910199,2cyclictest553-21snmpd11:57:423
7431879910198,3cyclictest553-21snmpd09:23:393
74318799101100,1cyclictest553-21snmpd08:27:373
7431849910199,2cyclictest553-21snmpd12:18:412
7431849910199,2cyclictest553-21snmpd11:18:402
7431849910199,2cyclictest553-21snmpd07:55:242
7431849910199,1cyclictest553-21snmpd11:57:242
7431799910198,2cyclictest553-21snmpd07:55:151
74317999101100,1cyclictest553-21snmpd09:21:481
7431759910199,2cyclictest553-21snmpd10:05:200
743203991000,99cyclictest0-21swapper/708:06:217
743203991000,100cyclictest0-21swapper/710:32:457
743203991000,100cyclictest0-21swapper/709:55:267
743203991000,100cyclictest0-21swapper/707:41:387
7432009910099,1cyclictest553-21snmpd09:52:256
743200991001,99cyclictest59-21ksoftirqd/612:21:576
743200991000,99cyclictest0-21swapper/609:30:146
743200991000,99cyclictest0-21swapper/609:00:206
743200991000,100cyclictest0-21swapper/612:06:246
743200991000,100cyclictest0-21swapper/611:40:266
743200991000,100cyclictest0-21swapper/611:40:266
743200991000,100cyclictest0-21swapper/611:30:526
743200991000,100cyclictest0-21swapper/610:35:156
743200991000,100cyclictest0-21swapper/607:27:476
743200991000,100cyclictest0-21swapper/607:27:476
743200991000,100cyclictest0-21swapper/607:22:206
7431969910099,1cyclictest553-21snmpd11:20:495
7431969910099,1cyclictest553-21snmpd09:16:535
7431969910099,1cyclictest553-21snmpd07:47:275
743196991000,99cyclictest0-21swapper/512:37:585
743196991000,99cyclictest0-21swapper/509:21:545
743196991000,99cyclictest0-21swapper/508:49:265
743196991000,99cyclictest0-21swapper/508:26:125
743196991000,100cyclictest0-21swapper/508:34:535
7431929910099,1cyclictest553-21snmpd12:35:314
7431929910098,2cyclictest553-21snmpd10:37:124
7431929910098,2cyclictest553-21snmpd08:12:344
7431929910097,3cyclictest553-21snmpd08:19:014
74319299100100,0cyclictest839880-21cat09:40:154
743192991000,99cyclictest0-21swapper/411:17:314
743192991000,99cyclictest0-21swapper/407:45:454
743192991000,98cyclictest0-21swapper/407:53:034
743192991000,0cyclictest0-21swapper/411:43:024
743192991000,0cyclictest0-21swapper/411:43:024
7431879910099,1cyclictest553-21snmpd12:20:083
7431879910099,1cyclictest553-21snmpd12:16:363
7431879910099,1cyclictest553-21snmpd11:25:353
7431879910099,1cyclictest553-21snmpd08:39:233
7431879910099,1cyclictest553-21snmpd08:01:453
7431879910099,1cyclictest553-21snmpd07:58:353
7431879910099,1cyclictest553-21snmpd07:46:033
7431879910098,2cyclictest553-21snmpd12:36:403
7431879910098,2cyclictest553-21snmpd09:33:223
7431849910099,1cyclictest553-21snmpd12:37:222
7431849910099,1cyclictest553-21snmpd08:53:202
7431849910099,1cyclictest553-21snmpd08:12:432
7431849910098,2cyclictest553-21snmpd10:41:152
743184991000,99cyclictest804856-21diskmemload12:23:392
743184991000,99cyclictest0-21swapper/211:27:502
743184991000,99cyclictest0-21swapper/211:11:312
743184991000,100cyclictest0-21swapper/211:01:402
743184991000,100cyclictest0-21swapper/209:51:552
7431799910099,1cyclictest553-21snmpd11:48:591
7431799910099,1cyclictest553-21snmpd10:14:051
7431799910099,1cyclictest553-21snmpd08:44:291
7431799910099,1cyclictest553-21snmpd08:38:111
7431799910099,1cyclictest553-21snmpd07:51:201
7431799910099,1cyclictest553-21snmpd07:32:351
7431799910099,1cyclictest0-21swapper/110:09:261
7431799910098,2cyclictest553-21snmpd09:56:591
7431799910097,2cyclictest553-21snmpd09:44:011
743179991000,99cyclictest804856-21diskmemload09:53:191
743179991000,99cyclictest0-21swapper/112:23:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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