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2026-04-15 - 11:50

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot8s (updated Wed Apr 15, 2026 00:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19367742122107,10sleep30-21swapper/319:05:513
19367682122106,10sleep60-21swapper/619:05:466
19370612121106,10sleep20-21swapper/219:09:582
1936800211891,22sleep00-21swapper/019:06:110
19367512116101,10sleep70-21swapper/719:05:307
19369852115100,10sleep10-21swapper/119:08:531
19367932115101,9sleep40-21swapper/419:06:084
1936924211398,10sleep50-21swapper/519:08:015
1937322991040,100cyclictest0-21swapper/600:38:466
193730599104100,3cyclictest31-21ksoftirqd/200:20:172
1937301991040,0cyclictest0-21swapper/119:35:151
19373229910399,1cyclictest553-21snmpd00:15:426
1937305991020,98cyclictest31-21ksoftirqd/223:08:262
1937305991020,101cyclictest0-21swapper/223:48:032
19373019910299,3cyclictest2193133-21cat00:05:151
19373229910199,2cyclictest553-21snmpd22:35:526
1937322991010,100cyclictest0-21swapper/621:15:026
19373189910199,2cyclictest553-21snmpd22:46:195
19373189910199,2cyclictest553-21snmpd19:59:115
19373189910199,2cyclictest553-21snmpd19:39:465
19373189910198,3cyclictest553-21snmpd22:10:155
19373189910198,2cyclictest553-21snmpd21:11:405
193731899101100,1cyclictest553-21snmpd22:00:175
1937318991010,99cyclictest0-21swapper/519:44:015
1937318991010,99cyclictest0-21swapper/519:30:305
1937318991010,101cyclictest0-21swapper/523:26:395
1937318991010,100cyclictest0-21swapper/520:42:085
1937318991010,100cyclictest0-21swapper/520:33:035
1937313991010,100cyclictest0-21swapper/420:52:554
1937313991010,100cyclictest0-21swapper/400:13:484
19373059910199,2cyclictest553-21snmpd23:37:202
19373059910199,2cyclictest553-21snmpd20:29:172
19373059910196,1cyclictest141rcu_preempt21:59:292
193730599101100,1cyclictest553-21snmpd00:04:002
1937305991010,100cyclictest0-21swapper/222:14:062
1937305991010,100cyclictest0-21swapper/221:53:382
19373019910198,3cyclictest553-21snmpd21:14:361
1937301991010,0cyclictest0-21swapper/100:34:521
1937325991000,99cyclictest0-21swapper/722:53:137
19373229910099,1cyclictest553-21snmpd23:57:576
19373229910099,1cyclictest553-21snmpd23:41:446
19373229910098,1cyclictest553-21snmpd19:39:286
1937322991000,99cyclictest2059309-21ssh22:03:266
1937322991000,99cyclictest0-21swapper/620:26:516
1937322991000,100cyclictest0-21swapper/600:21:156
19373189910099,1cyclictest553-21snmpd23:35:335
19373189910099,1cyclictest553-21snmpd21:59:325
19373189910099,1cyclictest553-21snmpd20:55:545
19373189910099,1cyclictest553-21snmpd20:51:255
19373189910098,2cyclictest553-21snmpd21:35:025
19373189910098,2cyclictest553-21snmpd21:23:285
19373189910098,2cyclictest553-21snmpd21:09:455
19373189910097,2cyclictest553-21snmpd22:35:585
1937318991000,99cyclictest0-21swapper/523:47:595
1937318991000,99cyclictest0-21swapper/519:22:505
19373139910099,1cyclictest553-21snmpd21:18:114
19373139910099,1cyclictest553-21snmpd20:35:414
1937313991000,99cyclictest0-21swapper/422:28:034
1937313991000,99cyclictest0-21swapper/420:57:094
1937313991000,100cyclictest0-21swapper/423:56:374
1937313991000,100cyclictest0-21swapper/423:37:444
1937313991000,100cyclictest0-21swapper/420:46:374
19373109910099,1cyclictest553-21snmpd23:13:283
19373109910099,1cyclictest553-21snmpd22:31:523
19373109910099,1cyclictest553-21snmpd21:49:413
19373109910099,1cyclictest553-21snmpd00:39:493
19373109910099,1cyclictest553-21snmpd00:32:343
19373109910098,1cyclictest553-21snmpd22:41:573
19373059910098,2cyclictest553-21snmpd19:26:372
1937305991000,99cyclictest0-21swapper/223:20:192
1937305991000,99cyclictest0-21swapper/222:36:212
1937305991000,99cyclictest0-21swapper/221:23:022
1937305991000,99cyclictest0-21swapper/221:16:562
1937305991000,99cyclictest0-21swapper/220:47:462
1937305991000,99cyclictest0-21swapper/219:58:172
1937305991000,99cyclictest0-21swapper/219:19:502
1937305991000,100cyclictest0-21swapper/223:17:092
1937305991000,100cyclictest0-21swapper/222:25:372
1937305991000,100cyclictest0-21swapper/222:15:152
1937305991000,100cyclictest0-21swapper/221:34:082
19373019910099,1cyclictest553-21snmpd19:14:321
19373019910098,2cyclictest553-21snmpd19:33:031
19373019910096,4cyclictest553-21snmpd00:20:481
1937301991000,99cyclictest1999634-21diskmemload22:50:351
1937301991000,99cyclictest0-21swapper/123:51:341
1937301991000,99cyclictest0-21swapper/122:08:231
1937301991000,99cyclictest0-21swapper/121:45:381
1937301991000,99cyclictest0-21swapper/119:42:151
1937301991000,100cyclictest0-21swapper/123:16:171
1937301991000,100cyclictest0-21swapper/122:04:091
1937301991000,100cyclictest0-21swapper/100:15:011
19372989910099,1cyclictest553-21snmpd22:22:400
19372989910099,1cyclictest553-21snmpd20:21:020
19372989910099,1cyclictest553-21snmpd20:17:470
19372989910099,1cyclictest553-21snmpd20:13:170
19372989910099,1cyclictest1938370-21cat19:10:130
19372989910098,1cyclictest553-21snmpd23:37:080
1937298991000,99cyclictest0-21swapper/022:58:320
1937298991000,99cyclictest0-21swapper/022:41:420
1937298991000,99cyclictest0-21swapper/022:10:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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