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2025-08-29 - 12:04

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot8s (updated Fri Aug 29, 2025 00:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
546262131116,9sleep40-21swapper/419:06:404
546612130116,9sleep10-21swapper/119:07:081
546062126112,9sleep20-21swapper/219:06:212
548112125110,10sleep70-21swapper/719:09:157
545282123111,7sleep00-21swapper/019:05:230
545892122107,10sleep30-21swapper/319:06:053
546102120106,9sleep60-21swapper/619:06:266
546002120106,9sleep50-21swapper/519:06:165
551159910299,3cyclictest546-21snmpd22:13:426
551159910299,3cyclictest546-21snmpd20:00:256
551159910299,3cyclictest546-21snmpd00:28:106
55115991020,99cyclictest0-21swapper/622:25:176
55115991020,0cyclictest0-21swapper/620:40:056
551129910299,3cyclictest546-21snmpd22:45:485
55112991020,100cyclictest117774-21diskmemload23:01:595
55112991020,0cyclictest0-21swapper/523:30:155
550939910299,3cyclictest546-21snmpd20:18:190
55118991010,101cyclictest0-21swapper/721:14:407
551159910198,3cyclictest546-21snmpd23:19:556
55115991010,99cyclictest0-21swapper/621:23:046
55115991010,100cyclictest0-21swapper/623:25:426
55115991010,100cyclictest0-21swapper/622:37:016
55115991010,100cyclictest0-21swapper/620:55:576
55115991010,100cyclictest0-21swapper/620:14:106
551129910199,2cyclictest546-21snmpd23:25:295
551129910199,1cyclictest546-21snmpd20:18:055
55112991010,1cyclictest0-21swapper/520:50:185
551049910199,2cyclictest546-21snmpd22:03:453
551049910199,2cyclictest546-21snmpd21:33:143
551049910199,2cyclictest546-21snmpd21:19:583
551049910199,2cyclictest546-21snmpd00:39:023
551049910198,3cyclictest546-21snmpd23:59:163
55099991010,100cyclictest0-21swapper/220:48:272
550939910199,2cyclictest546-21snmpd19:53:460
55093991010,101cyclictest0-21swapper/019:45:580
55093991010,101cyclictest0-21swapper/000:10:150
55093991010,100cyclictest0-21swapper/021:59:270
551189910099,1cyclictest0-21swapper/700:20:087
55118991000,99cyclictest0-21swapper/722:18:337
55118991000,99cyclictest0-21swapper/722:09:517
55118991000,100cyclictest0-21swapper/721:17:287
55118991000,100cyclictest0-21swapper/720:22:027
55118991000,100cyclictest0-21swapper/700:36:567
551159910099,1cyclictest546-21snmpd22:57:316
551159910099,1cyclictest546-21snmpd22:30:196
551159910099,1cyclictest546-21snmpd21:05:276
551159910099,1cyclictest546-21snmpd19:49:546
551159910097,3cyclictest546-21snmpd20:50:396
55115991000,100cyclictest0-21swapper/623:20:166
55115991000,100cyclictest0-21swapper/620:30:166
55115991000,100cyclictest0-21swapper/619:42:066
551129910099,1cyclictest546-21snmpd00:33:265
551129910099,1cyclictest180007-21cat22:10:145
551129910098,2cyclictest546-21snmpd21:16:285
551129910097,3cyclictest200174-21cat22:30:205
55112991000,1cyclictest0-21swapper/522:20:235
55112991000,100cyclictest0-21swapper/523:53:315
55112991000,100cyclictest0-21swapper/500:29:525
551079910099,1cyclictest546-21snmpd23:19:014
551079910099,1cyclictest546-21snmpd21:57:224
551079910099,1cyclictest546-21snmpd19:39:184
551079910099,1cyclictest0-21swapper/421:46:204
5510799100100,0cyclictest546-21snmpd22:47:574
55107991000,99cyclictest0-21swapper/423:43:444
55107991000,99cyclictest0-21swapper/420:46:394
55107991000,100cyclictest0-21swapper/421:12:014
55107991000,100cyclictest0-21swapper/420:35:144
55107991000,100cyclictest0-21swapper/400:04:454
55107991000,100cyclictest0-21swapper/400:04:454
551049910099,1cyclictest546-21snmpd22:44:543
551049910099,1cyclictest546-21snmpd22:18:023
551049910099,1cyclictest546-21snmpd20:28:553
551049910099,1cyclictest546-21snmpd20:20:353
551049910099,1cyclictest546-21snmpd00:16:243
551049910098,2cyclictest546-21snmpd22:55:163
551049910097,3cyclictest546-21snmpd21:43:443
550999910099,1cyclictest546-21snmpd22:49:462
550999910099,1cyclictest546-21snmpd21:13:282
550999910099,1cyclictest546-21snmpd20:13:052
550999910098,2cyclictest546-21snmpd21:26:132
550999910098,2cyclictest0-21swapper/221:45:342
55099991000,99cyclictest0-21swapper/223:49:542
55099991000,99cyclictest0-21swapper/221:01:062
55099991000,1cyclictest0-21swapper/222:26:362
55099991000,100cyclictest0-21swapper/223:33:112
55099991000,100cyclictest0-21swapper/222:51:192
550969910099,1cyclictest546-21snmpd23:52:161
550969910099,1cyclictest546-21snmpd23:37:301
550969910099,1cyclictest546-21snmpd23:27:501
550969910099,1cyclictest546-21snmpd22:42:151
550969910099,1cyclictest546-21snmpd21:09:371
550969910099,1cyclictest546-21snmpd20:12:081
550969910099,1cyclictest184972-21cat22:15:171
55096991000,1cyclictest0-21swapper/121:00:181
55096991000,100cyclictest0-21swapper/122:45:371
55096991000,100cyclictest0-21swapper/120:57:021
55096991000,100cyclictest0-21swapper/120:33:471
55096991000,100cyclictest0-21swapper/119:32:471
550939910098,2cyclictest546-21snmpd23:44:090
550939910098,2cyclictest546-21snmpd23:13:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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