You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-06 - 02:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8s (updated Fri Mar 06, 2026 00:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11013482119106,8sleep60-21swapper/619:09:536
11012752119105,9sleep70-21swapper/719:08:507
1101282211499,10sleep50-21swapper/519:08:575
1099242211499,10sleep00-21swapper/019:05:070
1101101211399,9sleep40-21swapper/419:06:234
1101043211398,10sleep20-21swapper/219:05:332
1101116211197,9sleep10-21swapper/119:06:361
1099245210893,10sleep30-21swapper/319:05:103
1101563991030,1cyclictest0-21swapper/023:47:000
11015929910299,2cyclictest553-21snmpd21:49:576
110159299102100,2cyclictest604517-21kworker/6:121:27:596
110159299102100,1cyclictest1289878-21kworker/6:200:07:146
11015859910299,3cyclictest553-21snmpd19:49:364
110158599102100,2cyclictest553-21snmpd22:07:094
11015689910299,2cyclictest553-21snmpd23:11:531
11015689910297,5cyclictest553-21snmpd22:53:141
1101568991020,100cyclictest0-21swapper/123:00:471
1101596991010,100cyclictest0-21swapper/722:18:137
1101596991010,0cyclictest0-21swapper/723:45:427
11015929910199,2cyclictest1289878-21kworker/6:223:42:066
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional