You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-11 - 15:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Wed Feb 11, 2026 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1056932136126,6sleep70-21swapper/707:06:507
1058022134105,9sleep20-21swapper/207:08:212
1056532131116,9sleep50-21swapper/507:06:165
1056802127112,10sleep30-21swapper/307:06:383
1055982124110,9sleep40-21swapper/407:05:274
1038002122108,9sleep00-21swapper/007:05:060
1058892121107,9sleep60-21swapper/607:09:386
1057432121107,9sleep10-21swapper/107:07:321
1061709910498,3cyclictest225245-21cat10:00:135
106170991030,100cyclictest0-21swapper/511:40:215
1061639910399,4cyclictest2579219-21snmpd09:54:013
1061739910299,3cyclictest2579219-21snmpd10:18:386
1061739910298,4cyclictest2579219-21snmpd12:29:426
106173991020,0cyclictest0-21swapper/612:37:266
1061709910299,3cyclictest2579219-21snmpd12:39:395
1061709910299,3cyclictest2579219-21snmpd09:54:285
1061599910299,3cyclictest2579219-21snmpd09:58:452
106159991020,101cyclictest0-21swapper/209:13:512
106150991020,100cyclictest0-21swapper/008:25:160
106178991010,99cyclictest0-21swapper/708:00:157
106178991010,100cyclictest0-21swapper/709:56:137
1061739910199,2cyclictest2579219-21snmpd07:33:596
106173991010,99cyclictest0-21swapper/609:31:066
106173991010,101cyclictest0-21swapper/611:10:576
1061709910199,2cyclictest2579219-21snmpd11:16:245
1061709910199,2cyclictest2579219-21snmpd11:06:515
106170991010,100cyclictest0-21swapper/509:46:255
106170991010,100cyclictest0-21swapper/507:45:325
1061639910199,2cyclictest2579219-21snmpd10:09:353
1061639910199,2cyclictest2579219-21snmpd09:59:403
1061639910199,2cyclictest2579219-21snmpd09:48:043
1061639910199,2cyclictest2579219-21snmpd09:09:383
1061639910199,2cyclictest2579219-21snmpd07:40:293
1061639910199,1cyclictest2579219-21snmpd09:40:343
1061639910198,3cyclictest2579219-21snmpd08:10:453
1061639910198,3cyclictest2579219-21snmpd07:18:043
1061599910198,3cyclictest2579219-21snmpd10:43:202
1061599910198,3cyclictest2579219-21snmpd10:43:202
106159991010,101cyclictest0-21swapper/210:55:182
106159991010,0cyclictest0-21swapper/210:49:212
1061549910199,2cyclictest2579219-21snmpd11:11:161
10615499101100,1cyclictest2579219-21snmpd07:30:321
1061509910199,2cyclictest2579219-21snmpd11:48:170
1061509910198,2cyclictest2579219-21snmpd07:20:050
1061509910197,4cyclictest2579219-21snmpd11:50:460
106150991010,100cyclictest0-21swapper/011:25:110
106178991000,99cyclictest0-21swapper/711:34:167
106178991000,99cyclictest0-21swapper/709:42:277
106178991000,99cyclictest0-21swapper/709:21:517
106178991000,98cyclictest0-21swapper/709:15:537
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional