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2026-02-18 - 15:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Wed Feb 18, 2026 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3778032127112,10sleep70-21swapper/707:08:107
3779282125112,8sleep30-21swapper/307:09:583
377861212596,9sleep20-21swapper/207:09:012
377806212595,9sleep10-21swapper/107:08:131
3778052122108,9sleep00-21swapper/007:08:120
3776672122106,10sleep40-21swapper/407:06:154
3778102120105,9sleep50-21swapper/507:08:165
3776962116101,9sleep60-21swapper/607:06:416
378353991020,100cyclictest0-21swapper/707:47:597
3783479910299,3cyclictest2579219-21snmpd07:23:526
378347991020,100cyclictest0-21swapper/609:49:026
3783329910299,2cyclictest2579219-21snmpd11:42:013
3783479910199,1cyclictest2579219-21snmpd10:37:296
3783479910198,3cyclictest2579219-21snmpd10:06:516
3783379910199,2cyclictest2579219-21snmpd09:30:134
37833299101100,1cyclictest2579219-21snmpd11:07:353
3783309910199,2cyclictest2579219-21snmpd09:03:482
37833099101100,1cyclictest2579219-21snmpd11:13:142
378330991010,100cyclictest0-21swapper/208:12:592
378324991010,100cyclictest0-21swapper/109:11:251
378324991010,100cyclictest0-21swapper/108:54:331
378353991000,99cyclictest0-21swapper/712:04:257
378353991000,99cyclictest0-21swapper/711:56:137
378353991000,100cyclictest0-21swapper/711:05:357
378353991000,100cyclictest0-21swapper/710:39:567
3783479910099,1cyclictest2579219-21snmpd10:34:316
3783479910099,1cyclictest2579219-21snmpd09:15:126
3783479910098,2cyclictest2579219-21snmpd07:18:126
3783479910098,1cyclictest425587-21cat08:40:126
3783479910098,1cyclictest2579219-21snmpd11:53:496
3783479910097,3cyclictest2579219-21snmpd09:54:306
3783439910099,1cyclictest660764-21cat12:30:125
3783439910099,1cyclictest2579219-21snmpd11:43:155
3783439910099,1cyclictest2579219-21snmpd11:28:245
3783439910099,1cyclictest2579219-21snmpd11:16:025
3783439910099,1cyclictest2579219-21snmpd10:51:315
3783439910099,1cyclictest2579219-21snmpd10:12:455
3783439910099,1cyclictest2579219-21snmpd09:54:155
3783439910099,1cyclictest2579219-21snmpd09:12:005
3783439910099,1cyclictest2579219-21snmpd08:40:445
3783439910099,1cyclictest2579219-21snmpd08:37:445
3783439910099,1cyclictest2579219-21snmpd08:11:535
3783439910099,1cyclictest2579219-21snmpd07:52:225
3783439910099,1cyclictest2579219-21snmpd07:49:375
3783439910099,1cyclictest2579219-21snmpd07:17:315
378343991000,99cyclictest0-21swapper/508:50:145
378343991000,99cyclictest0-21swapper/508:02:595
3783379910099,1cyclictest2579219-21snmpd11:18:474
3783379910099,1cyclictest2579219-21snmpd10:25:554
3783379910099,1cyclictest2579219-21snmpd09:40:404
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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