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2025-08-30 - 00:49

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Fri Aug 29, 2025 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9322312132118,9sleep00-21swapper/007:08:340
9322372128114,9sleep60-21swapper/607:08:416
9320772128113,10sleep30-21swapper/307:06:223
932179212698,9sleep20-21swapper/207:07:492
9321822124109,10sleep50-21swapper/507:07:525
9322022122108,9sleep70-21swapper/707:08:107
9321522121103,13sleep40-21swapper/407:07:274
9320482119108,7sleep10-21swapper/107:05:551
93275399115114,1cyclictest243-21kworker/7:111:33:117
932751991020,99cyclictest0-21swapper/611:35:256
932751991020,101cyclictest0-21swapper/610:34:326
9327459910299,1cyclictest546-21snmpd10:26:505
932745991020,0cyclictest0-21swapper/511:40:165
9327409910299,3cyclictest982522-21cat08:45:154
9327409910299,3cyclictest546-21snmpd10:03:484
932740991020,1cyclictest0-21swapper/409:30:184
932740991020,100cyclictest0-21swapper/411:52:154
9327379910299,3cyclictest546-21snmpd10:46:353
9327379910299,3cyclictest546-21snmpd09:36:543
932753991010,99cyclictest0-21swapper/710:35:117
9327519910199,2cyclictest546-21snmpd11:20:516
9327519910199,2cyclictest546-21snmpd09:50:216
9327519910199,1cyclictest546-21snmpd12:27:376
932751991010,101cyclictest0-21swapper/607:47:106
932751991010,0cyclictest0-21swapper/612:30:316
9327459910199,2cyclictest546-21snmpd07:51:595
9327409910199,2cyclictest546-21snmpd09:39:264
9327409910198,3cyclictest546-21snmpd09:44:544
9327409910197,4cyclictest1064160-21cat10:25:204
932740991010,101cyclictest0-21swapper/410:48:024
932740991010,100cyclictest0-21swapper/408:52:194
932740991010,0cyclictest0-21swapper/409:19:114
9327379910199,2cyclictest546-21snmpd09:31:233
9327299910199,2cyclictest546-21snmpd07:27:462
9327299910198,3cyclictest546-21snmpd10:59:262
9327299910198,3cyclictest546-21snmpd07:36:042
93272999101100,1cyclictest546-21snmpd07:47:322
932729991010,101cyclictest0-21swapper/209:27:292
932729991010,100cyclictest1112396-21ssh11:19:092
932729991010,100cyclictest1112396-21ssh11:19:082
932729991010,100cyclictest0-21swapper/212:29:172
932729991010,0cyclictest0-21swapper/207:51:022
93272299101100,1cyclictest546-21snmpd10:45:050
932753991000,99cyclictest0-21swapper/712:22:057
932753991000,99cyclictest0-21swapper/712:00:217
932753991000,99cyclictest0-21swapper/707:49:177
932753991000,98cyclictest0-21swapper/712:07:437
932753991000,1cyclictest0-21swapper/708:50:337
932753991000,0cyclictest0-21swapper/709:55:527
9327519910099,1cyclictest546-21snmpd12:10:536
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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