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2026-02-28 - 18:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Sat Feb 28, 2026 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29778012129101,9sleep60-21swapper/607:06:336
29778422123109,9sleep20-21swapper/207:07:092
29779802120106,9sleep10-21swapper/107:09:081
29779732120105,10sleep30-21swapper/307:09:023
29777642120105,10sleep70-21swapper/707:06:017
2978041211399,9sleep40-21swapper/407:09:584
2977878211398,10sleep00-21swapper/007:07:390
2977854211399,9sleep50-21swapper/507:07:205
29782729910298,4cyclictest553-21snmpd11:55:232
29782899910199,1cyclictest3213039-21kworker/6:111:52:316
29782899910199,1cyclictest3024611-21kworker/6:010:25:156
297828999101100,1cyclictest3213039-21kworker/6:112:28:266
297828999101100,1cyclictest3213039-21kworker/6:112:22:316
297828999101100,1cyclictest3213039-21kworker/6:112:22:316
297828999101100,1cyclictest3213039-21kworker/6:112:14:236
297828999101100,1cyclictest3213039-21kworker/6:112:07:406
297828999101100,1cyclictest3213039-21kworker/6:111:57:336
297828999101100,1cyclictest3168278-21kworker/6:211:41:036
297828999101100,1cyclictest3168278-21kworker/6:211:36:556
297828999101100,1cyclictest3168278-21kworker/6:211:33:556
297828999101100,1cyclictest3168278-21kworker/6:211:26:336
297828999101100,1cyclictest3168278-21kworker/6:211:20:366
297828999101100,1cyclictest3157175-21kworker/6:111:04:056
297828999101100,1cyclictest3024611-21kworker/6:010:56:126
297828999101100,1cyclictest3024611-21kworker/6:010:45:556
297828999101100,1cyclictest3024611-21kworker/6:010:40:136
297828999101100,1cyclictest3024611-21kworker/6:010:11:076
297828999101100,1cyclictest3024611-21kworker/6:010:05:426
297828999101100,1cyclictest3024611-21kworker/6:009:55:096
297828999101100,1cyclictest3024611-21kworker/6:009:52:216
297828999101100,1cyclictest3024611-21kworker/6:009:42:376
297828999101100,1cyclictest3024611-21kworker/6:009:38:396
297828999101100,1cyclictest3024611-21kworker/6:009:32:436
297828999101100,1cyclictest3024611-21kworker/6:009:27:516
297828999101100,1cyclictest3024611-21kworker/6:009:10:276
297828999101100,1cyclictest3011688-21kworker/6:208:20:196
2978284991010,100cyclictest0-21swapper/511:31:495
2978280991010,100cyclictest3062462-21apt-get09:30:114
297827599101100,1cyclictest553-21snmpd11:16:573
29782729910199,2cyclictest553-21snmpd12:36:002
29782729910198,3cyclictest553-21snmpd12:26:242
29782729910197,4cyclictest553-21snmpd11:13:562
2978272991010,100cyclictest0-21swapper/212:30:062
2978272991010,100cyclictest0-21swapper/209:58:292
29782679910199,2cyclictest553-21snmpd10:41:591
2978267991010,100cyclictest0-21swapper/112:33:541
29782639910199,2cyclictest553-21snmpd11:54:140
2978263991010,101cyclictest0-21swapper/009:15:250
2978263991010,0cyclictest0-21swapper/009:03:120
2978293991000,99cyclictest0-21swapper/710:44:357
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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