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2025-12-20 - 05:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Sat Dec 20, 2025 00:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6918262126112,9sleep40-21swapper/419:09:584
6917122126110,10sleep10-21swapper/119:08:191
6917912125111,9sleep60-21swapper/619:09:296
6916532125110,10sleep70-21swapper/719:07:307
6897142123109,9sleep20-21swapper/219:05:072
6917972121106,9sleep30-21swapper/319:09:333
6917902120106,9sleep50-21swapper/519:09:275
691747212092,22sleep00-21swapper/019:08:500
69206199105102,3cyclictest31-21ksoftirqd/222:42:082
69206199104101,2cyclictest31-21ksoftirqd/200:06:422
692061991032,101cyclictest31-21ksoftirqd/223:00:542
692061991031,1cyclictest141rcu_preempt23:30:152
69207799102100,2cyclictest0-21swapper/623:06:496
692069991020,100cyclictest0-21swapper/422:59:464
6920669910299,3cyclictest556-21snmpd21:51:313
692061991021,101cyclictest31-21ksoftirqd/222:34:022
692061991021,100cyclictest31-21ksoftirqd/200:21:242
69206199102101,0cyclictest31-21ksoftirqd/200:19:082
692061991020,1cyclictest31-21ksoftirqd/223:13:542
692061991020,100cyclictest31-21ksoftirqd/200:10:332
692061991020,0cyclictest141rcu_preempt22:05:102
692081991010,99cyclictest0-21swapper/721:54:587
692081991010,101cyclictest0-21swapper/723:48:267
692081991010,101cyclictest0-21swapper/720:14:527
692081991010,100cyclictest0-21swapper/721:07:097
6920779910199,1cyclictest556-21snmpd22:35:216
6920729910199,2cyclictest556-21snmpd19:25:215
69207299101100,1cyclictest556-21snmpd22:09:235
692072991010,100cyclictest0-21swapper/522:02:115
6920699910199,2cyclictest556-21snmpd21:30:434
6920699910198,3cyclictest556-21snmpd20:45:534
6920699910198,3cyclictest556-21snmpd20:34:234
6920699910198,2cyclictest556-21snmpd22:08:084
692069991010,101cyclictest0-21swapper/422:17:024
692069991010,101cyclictest0-21swapper/419:39:344
692069991010,0cyclictest0-21swapper/400:38:284
6920669910199,2cyclictest556-21snmpd21:23:543
6920669910199,2cyclictest556-21snmpd19:27:493
692061991011,1cyclictest840511-21kworker/2:223:05:262
692061991011,100cyclictest3139828-21kworker/2:122:01:422
692061991011,100cyclictest31-21ksoftirqd/222:38:502
692061991011,100cyclictest31-21ksoftirqd/222:19:562
69206199101101,0cyclictest3139828-21kworker/2:121:42:502
69206199101100,1cyclictest931365-21kworker/2:000:34:042
69206199101100,1cyclictest840511-21kworker/2:223:25:142
69206199101100,1cyclictest840511-21kworker/2:222:58:212
69206199101100,1cyclictest3139828-21kworker/2:121:00:182
69206199101100,1cyclictest0-21swapper/223:57:562
69206199101100,1cyclictest0-21swapper/222:22:132
692061991010,101cyclictest3139828-21kworker/2:121:11:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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