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2025-12-30 - 13:13

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Tue Dec 30, 2025 00:44:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25200702130115,10sleep30-21swapper/319:08:473
25198612130103,22sleep00-21swapper/019:05:470
25200332126111,10sleep40-21swapper/419:08:164
2520048212494,10sleep10-21swapper/119:08:291
25198682124110,9sleep70-21swapper/719:05:537
25198342123109,9sleep20-21swapper/219:05:252
25200442119105,9sleep60-21swapper/619:08:256
25200162119105,9sleep50-21swapper/519:08:005
2520379991040,100cyclictest0-21swapper/023:20:150
25203799910399,4cyclictest2783364-21cat00:30:160
2520407991020,100cyclictest0-21swapper/722:13:337
2520384991020,100cyclictest0-21swapper/119:14:041
25203799910299,3cyclictest556-21snmpd23:09:200
25203799910299,2cyclictest2688401-21cat22:55:150
2520407991010,99cyclictest0-21swapper/719:47:537
2520407991010,101cyclictest0-21swapper/722:19:097
25204049910199,2cyclictest556-21snmpd21:29:446
252040499101100,1cyclictest556-21snmpd00:39:536
252040499101100,1cyclictest168617-21kworker/6:022:08:036
252040499101100,1cyclictest168617-21kworker/6:021:33:086
25203999910199,2cyclictest556-21snmpd22:24:385
25203999910198,3cyclictest556-21snmpd00:35:205
2520399991010,101cyclictest0-21swapper/522:30:485
2520399991010,101cyclictest0-21swapper/500:07:075
25203959910199,1cyclictest556-21snmpd00:01:314
2520395991010,100cyclictest0-21swapper/422:48:314
25203919910199,2cyclictest556-21snmpd19:46:523
25203889910199,2cyclictest556-21snmpd19:50:172
252038899101100,1cyclictest556-21snmpd19:29:482
25203849910199,2cyclictest556-21snmpd22:12:411
25203849910199,2cyclictest556-21snmpd22:06:261
2520384991010,99cyclictest0-21swapper/121:00:311
2520384991010,99cyclictest0-21swapper/120:47:331
2520384991010,101cyclictest0-21swapper/121:35:021
2520384991010,101cyclictest0-21swapper/119:19:061
25203799910199,2cyclictest556-21snmpd22:14:290
25203799910199,2cyclictest556-21snmpd19:24:360
25203799910198,3cyclictest2524633-21cat19:15:150
2520379991010,0cyclictest0-21swapper/020:14:040
2520407991000,99cyclictest0-21swapper/721:56:117
2520407991000,99cyclictest0-21swapper/721:03:097
25204049910099,1cyclictest556-21snmpd23:28:136
25204049910099,1cyclictest556-21snmpd22:50:016
25204049910099,1cyclictest556-21snmpd20:23:186
25204049910099,1cyclictest168617-21kworker/6:023:45:486
25204049910099,1cyclictest168617-21kworker/6:023:30:216
25204049910099,1cyclictest168617-21kworker/6:022:38:006
25204049910099,1cyclictest168617-21kworker/6:022:10:116
25204049910099,1cyclictest168617-21kworker/6:021:15:446
25204049910099,1cyclictest168617-21kworker/6:021:05:156
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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