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2025-12-21 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot1.osadl.org (updated Sun Dec 21, 2025 01:40:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210:44:529084
16,10:44:219083
36,10:44:219082
32,10:44:219081
33,10:44:219080
33,10:44:219079
30,10:44:219078
17,10:44:219077
34,10:44:219076
36,10:44:219075
29,10:44:219074
31,10:44:219073
010:44:219069
0,10:44:219068
0,10:44:219067
0,10:44:219066
0,10:44:219065
0,10:44:219064
0,10:44:219063
0,10:44:219062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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