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2025-12-24 - 16:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Wed Dec 24, 2025 13:45:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210:44:529084
16,10:44:219083
36,10:44:219082
32,10:44:219081
33,10:44:219080
33,10:44:219079
30,10:44:219078
17,10:44:219077
34,10:44:219076
36,10:44:219075
29,10:44:219074
31,10:44:219073
010:44:219069
0,10:44:219068
0,10:44:219067
0,10:44:219066
0,10:44:219065
0,10:44:219064
0,10:44:219063
0,10:44:219062
0,10:44:219061
0,10:44:219060
0,10:44:219059
0,10:44:219058
0,10:44:219057
0,10:44:219056
0,10:44:219055
0,10:44:219054
0,10:44:219053
0,10:44:219052
0,10:44:219051
0,10:44:219050
0,10:44:219049
0,10:44:219048
0,10:44:219047
0,10:44:219046
0,10:44:219045
0,10:44:219044
0,10:44:219043
0,10:44:219042
0,10:44:219041
0,10:44:219040
0,10:44:219039
0,10:44:219038
0,10:44:219037
0,10:44:219036
0,10:44:219035
0,10:44:219034
0,10:44:219033
0,10:44:219032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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