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2025-05-02 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Fri May 02, 2025 01:39:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210:20:269084
16,10:19:559083
36,10:19:559082
32,10:19:559081
33,10:19:559080
33,10:19:559079
30,10:19:559078
17,10:19:559077
34,10:19:559076
36,10:19:559075
29,10:19:559074
31,10:19:559073
010:19:559069
0,10:19:559068
0,10:19:559067
0,10:19:559066
0,10:19:559065
0,10:19:559064
0,10:19:559063
0,10:19:559062
0,10:19:559061
0,10:19:559060
0,10:19:559059
0,10:19:559058
0,10:19:559057
0,10:19:559056
0,10:19:559055
0,10:19:559054
0,10:19:559053
0,10:19:559052
0,10:19:559051
0,10:19:559050
0,10:19:559049
0,10:19:559048
0,10:19:559047
0,10:19:559046
0,10:19:559045
0,10:19:559044
0,10:19:559043
0,10:19:559042
0,10:19:559041
0,10:19:559040
0,10:19:559039
0,10:19:559038
0,10:19:559037
0,10:19:559036
0,10:19:559035
0,10:19:559034
0,10:19:559033
0,10:19:559032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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