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2026-07-16 - 16:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Thu Jul 16, 2026 13:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3212:08:569084
16,12:08:249083
36,12:08:249082
32,12:08:249081
33,12:08:249080
33,12:08:249079
30,12:08:249078
17,12:08:249077
34,12:08:249076
36,12:08:249075
29,12:08:249074
31,12:08:249073
012:08:249069
0,12:08:249068
0,12:08:249067
0,12:08:249066
0,12:08:249065
0,12:08:249064
0,12:08:249063
0,12:08:249062
0,12:08:249061
0,12:08:249060
0,12:08:249059
0,12:08:249058
0,12:08:249057
0,12:08:249056
0,12:08:249055
0,12:08:249054
0,12:08:249053
0,12:08:249052
0,12:08:249051
0,12:08:249050
0,12:08:249049
0,12:08:249048
0,12:08:249047
0,12:08:249046
0,12:08:249045
0,12:08:249044
0,12:08:249043
0,12:08:249042
0,12:08:249041
0,12:08:249040
0,12:08:249039
0,12:08:249038
0,12:08:249037
0,12:08:249036
0,12:08:249035
0,12:08:249034
0,12:08:249033
0,12:08:249032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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