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2025-12-16 - 21:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Tue Dec 16, 2025 13:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3210:42:419084
16,10:42:109083
36,10:42:109082
32,10:42:109081
33,10:42:109080
33,10:42:109079
30,10:42:109078
17,10:42:109077
34,10:42:109076
36,10:42:109075
29,10:42:109074
31,10:42:109073
010:42:109069
0,10:42:109068
0,10:42:109067
0,10:42:109066
0,10:42:109065
0,10:42:109064
0,10:42:109063
0,10:42:109062
0,10:42:109061
0,10:42:109060
0,10:42:109059
0,10:42:109058
0,10:42:109057
0,10:42:109056
0,10:42:109055
0,10:42:109054
0,10:42:109053
0,10:42:109052
0,10:42:109051
0,10:42:109050
0,10:42:109049
0,10:42:109048
0,10:42:109047
0,10:42:109046
0,10:42:109045
0,10:42:109044
0,10:42:109043
0,10:42:109042
0,10:42:109041
0,10:42:109040
0,10:42:109039
0,10:42:109038
0,10:42:109037
0,10:42:109036
0,10:42:109035
0,10:42:109034
0,10:42:109033
0,10:42:109032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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