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2026-03-14 - 14:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Mar 14, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1409226956,8sleep00-21swapper/019:07:330
1394426856,8sleep10-21swapper/119:06:001
14451993737,0cyclictest0-21swapper/123:01:571
14450993210,21cyclictest0-21swapper/023:22:200
1445199310,1cyclictest0-21swapper/121:48:551
400023010,0sleep00-21swapper/023:33:130
1445199300,0cyclictest0-21swapper/123:45:061
1445099300,1cyclictest0-21swapper/022:03:090
1427123027,1sleep00-21swapper/019:09:240
14451992929,0cyclictest0-21swapper/121:27:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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