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2025-12-21 - 02:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Dec 20, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1107426957,8sleep10-21swapper/107:05:311
1129226649,8sleep00-21swapper/007:07:490
11680992810,16cyclictest0-21swapper/111:10:131
1168099280,11cyclictest0-21swapper/108:30:211
11679992810,0cyclictest0-21swapper/010:09:520
11679992727,0cyclictest0-21swapper/007:55:180
1167999270,1cyclictest22474-21irqstats09:00:130
11680992626,0cyclictest0-21swapper/111:54:191
11680992610,16cyclictest0-21swapper/111:48:261
1168099250,23cyclictest0-21swapper/112:24:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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