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2026-04-14 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Apr 14, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
862727932,41sleep00-21swapper/007:04:310
941327057,8sleep10-21swapper/107:07:411
263002530,0sleep00-21swapper/009:11:500
9738993417,17cyclictest0-21swapper/108:18:521
9738993417,17cyclictest0-21swapper/108:18:521
9738992727,0cyclictest0-21swapper/110:59:311
9738992710,8cyclictest0-21swapper/108:59:211
973799271,25cyclictest0-21swapper/010:44:250
9737992710,16cyclictest0-21swapper/011:16:420
9738992610,1cyclictest0-21swapper/109:17:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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