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2025-05-09 - 05:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri May 09, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48772810,2sleep1807299cyclictest20:23:311
219502800,0sleep00-21swapper/022:32:300
770627135,31sleep10-21swapper/119:06:201
80502700,1sleep10-21swapper/123:38:321
762326957,8sleep00-21swapper/019:05:270
8071994010,29cyclictest0-21swapper/023:21:240
8072993510,22cyclictest27336-21kworker/u4:000:12:251
8072993030,0cyclictest0-21swapper/121:16:061
8071992918,4cyclictest7-21ksoftirqd/019:48:270
8071992910,1cyclictest0-21swapper/021:39:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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