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2026-04-26 - 05:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sun Apr 26, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
570527158,8sleep00-21swapper/019:08:580
537826956,8sleep10-21swapper/119:05:331
113182630,0sleep111319-21sh22:59:561
5900993511,14cyclictest91rcu_preempt00:37:571
5900993417,2cyclictest91rcu_preempt19:44:251
5900993413,2cyclictest91rcu_preempt19:09:171
590099339,2cyclictest91rcu_preempt21:31:201
590099335,5cyclictest91rcu_preempt23:41:231
590099333,4cyclictest91rcu_preempt19:34:191
590099329,11cyclictest91rcu_preempt20:29:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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