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2026-03-18 - 04:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Mar 18, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1266227562,8sleep10-21swapper/119:05:131
1264626754,8sleep00-21swapper/019:05:020
13242993331,1cyclictest231ktimersoftd/121:09:351
13241993130,1cyclictest0-21swapper/022:48:290
13242992910,17cyclictest0-21swapper/122:01:531
1324199290,0cyclictest0-21swapper/023:19:470
13241992810,9cyclictest0-21swapper/023:41:410
1324199280,15cyclictest0-21swapper/021:44:290
1324299263,22cyclictest0-21swapper/119:24:331
13242992610,9cyclictest0-21swapper/123:44:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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