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2026-02-26 - 07:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Feb 26, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
748527361,7sleep00-21swapper/019:08:330
735727149,8sleep10-21swapper/119:07:121
182602660,1sleep10-21swapper/120:59:461
59882450,1sleep121439-21diskmemload22:14:481
775899397,3cyclictest9429-21apache_accesses23:04:410
7758993838,0cyclictest0-21swapper/023:36:260
775899353,1cyclictest91rcu_preempt21:54:010
775899339,8cyclictest7-21ksoftirqd/022:29:340
775899324,4cyclictest91rcu_preempt00:29:380
775899323,0cyclictest91rcu_preempt22:35:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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