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2026-03-01 - 07:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Feb 28, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2962527357,8sleep00-21swapper/007:07:420
200712710,0sleep020069-21seq09:19:450
2805727057,8sleep10-21swapper/107:04:441
266742680,1sleep10-21swapper/110:57:581
309562670,1sleep10-21swapper/107:09:471
125832670,1sleep00-21swapper/009:09:460
29979993210,20cyclictest0-21swapper/007:26:490
2998099290,28cyclictest23400-21taskset10:09:261
29980992827,0cyclictest231ktimersoftd/112:11:341
29980992826,1cyclictest24-21ksoftirqd/108:59:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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