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2025-12-13 - 11:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Dec 13, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1984726935,29sleep10-21swapper/119:05:031
2154926856,8sleep00-21swapper/019:09:280
21783993510,24cyclictest0-21swapper/119:18:501
21783992626,0cyclictest0-21swapper/120:07:471
21782992617,9cyclictest0-21swapper/023:59:270
21783992525,0cyclictest0-21swapper/121:06:581
2178399250,9cyclictest0-21swapper/120:10:121
2178299253,19cyclictest0-21swapper/019:53:430
21782992523,1cyclictest7-21ksoftirqd/022:40:000
21783992419,5cyclictest862-21apache220:48:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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