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2025-11-07 - 21:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Nov 07, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17622690,0sleep00-21swapper/011:15:020
1044726755,8sleep10-21swapper/107:04:161
1043426755,8sleep00-21swapper/007:04:070
252772630,0sleep10-21swapper/112:24:161
10878993610,22cyclictest0-21swapper/010:19:220
10878993410,0cyclictest0-21swapper/009:22:070
10878993210,2cyclictest0-21swapper/010:35:300
10879993129,1cyclictest0-21swapper/109:52:421
1087999300,1cyclictest11108-21munin-run12:06:511
10879992824,3cyclictest5083-21kworker/u4:112:21:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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