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2026-04-10 - 19:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Apr 10, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324952730,1sleep00-21swapper/012:29:250
342526849,8sleep00-21swapper/007:07:260
272492680,0sleep10-21swapper/110:51:061
184826755,8sleep10-21swapper/107:04:191
166602640,1sleep10-21swapper/111:21:471
3778993410,1cyclictest0-21swapper/109:48:481
3777993010,19cyclictest0-21swapper/010:11:040
3777992820,3cyclictest81ktimersoftd/007:59:260
3777992725,2cyclictest0-21swapper/012:04:330
3777992713,5cyclictest636-21nscd09:55:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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