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2026-09-21 - 17:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Sep 21, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3094427057,8sleep10-21swapper/107:06:161
3066326451,8sleep00-21swapper/007:03:190
304212500,0sleep03127799cyclictest11:06:130
3127899290,18cyclictest26064-21kworker/u4:112:10:271
31277992928,1cyclictest0-21swapper/012:06:590
31278992828,0cyclictest0-21swapper/112:36:441
31278992710,11cyclictest0-21swapper/109:30:171
31277992710,16cyclictest0-21swapper/011:21:020
31277992710,10cyclictest0-21swapper/009:35:350
31278992618,3cyclictest8729-21apache212:27:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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