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2025-11-18 - 00:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Nov 17, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
492221000,0sleep10-21swapper/107:27:011
2894427057,8sleep00-21swapper/007:03:570
2884226955,9sleep10-21swapper/107:02:541
114862660,1sleep110819-21/usr/sbin/munin11:52:051
29398993210,18cyclictest0-21swapper/112:25:061
29398993010,2cyclictest0-21swapper/110:03:091
29398993010,14cyclictest0-21swapper/111:17:521
2939899290,25cyclictest18476-21/usr/sbin/munin08:02:001
29397992916,13cyclictest0-21swapper/008:49:320
29398992824,3cyclictest21786-21ssh09:19:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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