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2026-04-30 - 06:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Apr 29, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
427226955,9sleep10-21swapper/107:06:341
320832670,0sleep10-21swapper/112:11:531
429426552,8sleep00-21swapper/007:06:470
43022630,0sleep00-21swapper/010:12:450
274172460,0sleep00-21swapper/008:04:250
4694993710,0cyclictest0-21swapper/111:42:101
4693993410,22cyclictest0-21swapper/009:45:010
4694993333,0cyclictest0-21swapper/110:02:101
4694993333,0cyclictest0-21swapper/108:04:311
4694993018,11cyclictest14580-21apache211:37:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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