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2026-07-13 - 11:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Jul 13, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260728053,22sleep00-21swapper/019:04:170
200022720,1sleep10-21swapper/100:31:451
296626652,9sleep10-21swapper/119:08:031
318499310,3cyclictest12943-21tr20:58:251
3183993110,20cyclictest0-21swapper/021:59:580
3184992929,0cyclictest0-21swapper/100:01:491
318499280,25cyclictest28521-21ssh22:41:291
3183992810,13cyclictest0-21swapper/022:06:400
318499270,0cyclictest0-21swapper/122:44:351
318399270,2cyclictest0-21swapper/023:54:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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