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2026-03-25 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Mar 25, 2026 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56342910,0sleep10-21swapper/121:46:291
2817627153,9sleep10-21swapper/119:06:171
2826526754,8sleep00-21swapper/019:07:130
296942660,1sleep129696-21proc_pri22:19:371
28648994410,33cyclictest0-21swapper/119:45:021
28648994310,32cyclictest0-21swapper/120:59:531
28648994210,31cyclictest9850-21diskmemload22:13:011
28648994210,31cyclictest0-21swapper/123:19:311
28648994210,31cyclictest0-21swapper/122:30:261
28648994210,31cyclictest0-21swapper/121:39:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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