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2026-04-25 - 05:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Apr 25, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1427528035,40sleep00-21swapper/019:07:530
1410827049,16sleep10-21swapper/119:06:091
14570994310,3cyclictest100250irq/107-eth1-rx00:24:411
14570994010,6cyclictest0-21swapper/122:24:181
59672380,0sleep00-21swapper/022:01:290
14570993710,26cyclictest0-21swapper/123:04:031
14570993710,26cyclictest0-21swapper/100:34:371
14570993510,24cyclictest0-21swapper/122:42:211
1457099350,3cyclictest20066-21memory22:19:201
14570993410,23cyclictest0-21swapper/121:46:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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