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2026-01-06 - 03:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Jan 06, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
108052720,0sleep00-21swapper/023:08:070
3171627057,9sleep10-21swapper/119:07:291
319712680,0sleep10-21swapper/122:12:031
3161725933,22sleep00-21swapper/019:06:280
32121993210,13cyclictest0-21swapper/021:54:470
32121993010,14cyclictest0-21swapper/000:03:210
3212299291,6cyclictest24-21ksoftirqd/122:21:051
32122992914,2cyclictest91rcu_preempt00:22:061
32122992827,0cyclictest24-21ksoftirqd/122:05:041
32122992827,0cyclictest24-21ksoftirqd/122:02:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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