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2025-10-15 - 13:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Oct 15, 2025 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2056821210,1sleep02105399cyclictest22:17:010
270602710,1sleep10-21swapper/121:42:151
2069127158,8sleep00-21swapper/019:05:060
2045127057,8sleep10-21swapper/119:02:381
21054993210,0cyclictest0-21swapper/121:41:481
21053993110,20cyclictest0-21swapper/023:28:100
21053993110,20cyclictest0-21swapper/000:19:420
21053993011,12cyclictest97750irq/106-eth1-rx21:27:410
21053992927,1cyclictest81ktimersoftd/022:55:120
21053992910,19cyclictest0-21swapper/000:14:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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