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2026-04-25 - 17:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Apr 25, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1618827957,17sleep10-21swapper/107:06:561
126132780,2sleep11657599cyclictest10:05:561
1618426554,7sleep00-21swapper/007:06:530
71642640,0sleep00-21swapper/011:21:070
16574993010,0cyclictest0-21swapper/011:18:440
16575992919,10cyclictest0-21swapper/110:20:231
1657599290,28cyclictest0-21swapper/109:21:391
1657599290,0cyclictest0-21swapper/109:27:391
16574992928,0cyclictest7-21ksoftirqd/007:19:060
1657599280,3cyclictest0-21swapper/111:32:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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