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2026-02-05 - 05:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Feb 04, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33392740,0sleep00-21swapper/010:49:540
1065827258,9sleep00-21swapper/007:07:380
1042726757,5sleep10-21swapper/107:05:141
117092660,1sleep10-21swapper/111:46:001
27612590,1sleep00-21swapper/011:32:460
1103299379,4cyclictest91rcu_preempt11:38:001
11032993635,0cyclictest24-21ksoftirqd/112:30:131
11032993616,11cyclictest91rcu_preempt09:22:491
11032993615,5cyclictest91rcu_preempt07:19:541
11032993534,1cyclictest24-21ksoftirqd/112:24:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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