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2026-05-16 - 10:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat May 16, 2026 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2888726957,8sleep00-21swapper/019:07:200
2888726957,8sleep00-21swapper/019:07:200
2871526956,8sleep10-21swapper/119:05:331
2871526956,8sleep10-21swapper/119:05:331
253992680,0sleep00-21swapper/022:53:210
29224993413,15cyclictest24-21ksoftirqd/122:16:381
29223993310,1cyclictest0-21swapper/021:43:270
2922399320,29cyclictest21175-21kworker/0:220:28:530
29224993030,0cyclictest0-21swapper/121:16:001
2922399303,26cyclictest21175-21kworker/0:219:28:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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