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2025-11-25 - 01:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Nov 24, 2025 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1866326754,8sleep00-21swapper/007:02:410
1729326653,8sleep10-21swapper/107:01:481
19236994010,4cyclictest0-21swapper/110:21:391
19236993410,3cyclictest0-21swapper/107:08:181
19235993310,15cyclictest0-21swapper/009:53:460
1923699281,26cyclictest0-21swapper/107:46:581
19235992810,2cyclictest0-21swapper/009:48:320
19236992723,3cyclictest1111-21runrttasks11:33:511
19236992722,4cyclictest29075-21apache209:28:561
19236992721,3cyclictest29047-21apache209:36:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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