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2025-11-28 - 02:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Nov 27, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325892760,0sleep00-21swapper/009:46:380
1941427149,17sleep00-21swapper/007:02:390
1967427050,8sleep10-21swapper/107:05:221
1998599339,3cyclictest91rcu_preempt11:09:251
1998599331,3cyclictest2396-21munin-run10:31:441
19985993310,12cyclictest0-21swapper/111:39:111
19984993210,21cyclictest0-21swapper/012:07:420
19985992929,0cyclictest24-21ksoftirqd/109:21:101
1998599292,2cyclictest91rcu_preempt09:13:431
1998599290,0cyclictest91rcu_preempt09:26:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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