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2026-04-15 - 23:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Apr 15, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1797027047,17sleep10-21swapper/107:04:281
1873926754,8sleep00-21swapper/007:07:250
4212450,0sleep00-21swapper/012:08:350
19086993333,0cyclictest0-21swapper/011:16:510
19086993333,0cyclictest0-21swapper/009:21:450
19086993210,21cyclictest0-21swapper/012:37:150
19086993110,15cyclictest0-21swapper/008:34:440
1890723027,1sleep00-21swapper/007:09:090
19086992826,1cyclictest0-21swapper/010:33:210
1908699281,26cyclictest0-21swapper/012:24:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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