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2026-08-10 - 12:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Aug 10, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
502427152,7sleep10-21swapper/119:03:381
196322690,0sleep00-21swapper/019:43:270
511026756,7sleep00-21swapper/019:04:290
5645993610,0cyclictest0-21swapper/000:09:520
5645993310,20cyclictest0-21swapper/000:33:560
5646993030,0cyclictest0-21swapper/100:18:261
5646993022,4cyclictest0-21swapper/120:43:321
5646992928,1cyclictest0-21swapper/120:28:341
5646992910,10cyclictest0-21swapper/100:31:261
5645992910,5cyclictest0-21swapper/021:12:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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