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2025-12-09 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Dec 09, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2091226854,9sleep10-21swapper/119:04:501
1933226754,8sleep00-21swapper/019:01:440
91702610,1sleep10-21swapper/121:14:511
21266993310,22cyclictest0-21swapper/022:40:570
21266993010,2cyclictest0-21swapper/000:11:440
21266993010,15cyclictest0-21swapper/023:17:230
2126799290,0cyclictest0-21swapper/121:48:211
21267992810,1cyclictest0-21swapper/121:17:281
21266992820,5cyclictest5337-21apache222:46:120
21266992811,12cyclictest97950irq/108-eth1-tx21:57:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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