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2026-03-08 - 11:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sun Mar 08, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2213327261,7sleep10-21swapper/119:08:031
2195826553,8sleep00-21swapper/019:06:140
247972630,0sleep024798-21cat19:14:410
2244799300,29cyclictest0-21swapper/122:02:411
22446993026,2cyclictest0-21swapper/021:54:000
22446992919,10cyclictest2750-21kworker/0:119:52:410
22447992811,7cyclictest0-21swapper/120:29:541
22447992710,11cyclictest0-21swapper/119:49:461
22446992710,13cyclictest0-21swapper/021:20:190
2244699270,26cyclictest0-21swapper/000:34:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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