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2026-07-27 - 13:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Jul 27, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151402950,0sleep1231ktimersoftd/123:46:281
915527354,14sleep00-21swapper/019:03:400
209192710,0sleep10-21swapper/121:45:161
36622700,0sleep10-21swapper/122:05:111
953126854,9sleep10-21swapper/119:03:431
169582650,0sleep00-21swapper/000:32:220
10267993813,24cyclictest0-21swapper/122:23:341
10267993210,0cyclictest0-21swapper/122:29:031
10267993117,14cyclictest0-21swapper/119:09:151
10267992926,2cyclictest604-21ssh00:10:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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