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2025-12-05 - 04:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Dec 05, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3246327254,8sleep00-21swapper/019:01:420
3247026854,9sleep10-21swapper/119:01:471
174232640,0sleep00-21swapper/021:52:030
295302630,1sleep00-21swapper/022:53:450
89352590,0sleep10-21swapper/123:10:511
135402560,2sleep1201899cyclictest21:46:571
2018993710,0cyclictest0-21swapper/123:27:351
2018993310,21cyclictest0-21swapper/122:26:291
2018992929,0cyclictest0-21swapper/123:05:541
2018992910,15cyclictest0-21swapper/121:54:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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