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2026-05-02 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat May 02, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1088127158,8sleep00-21swapper/019:06:000
241152700,1sleep10-21swapper/121:04:201
1092027057,8sleep10-21swapper/119:06:251
248812640,0sleep00-21swapper/022:29:230
54312630,0sleep10-21swapper/123:28:591
162282450,0sleep01135299cyclictest19:19:170
11352993210,20cyclictest0-21swapper/021:25:040
11352993010,20cyclictest0-21swapper/021:17:130
11353992810,14cyclictest0-21swapper/121:18:011
11353992810,10cyclictest0-21swapper/123:17:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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