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2026-04-18 - 00:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Apr 17, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
235062720,0sleep10-21swapper/112:19:531
3272127150,8sleep10-21swapper/107:05:541
207112690,0sleep00-21swapper/012:16:490
114512660,1sleep10-21swapper/110:34:001
47926553,8sleep00-21swapper/007:08:100
240722610,0sleep00-21swapper/009:19:570
80799310,30cyclictest75892sleep111:13:501
80699311,29cyclictest10665-21kworker/0:107:36:150
80699291,27cyclictest0-21swapper/011:54:190
80699290,28cyclictest0-21swapper/010:18:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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