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2025-06-29 - 00:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Jun 28, 2025 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1880327249,17sleep10-21swapper/107:03:121
237732690,0sleep10-21swapper/111:41:331
1967026653,8sleep00-21swapper/007:06:340
290222630,0sleep10-21swapper/109:42:501
19975993533,1cyclictest7-21ksoftirqd/011:33:170
19975993211,3cyclictest91rcu_preempt08:38:160
19976993110,20cyclictest0-21swapper/107:30:501
1997599313,27cyclictest0-21swapper/009:57:210
19975993029,1cyclictest7-21ksoftirqd/010:13:080
1997599298,2cyclictest91rcu_preempt09:29:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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