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2026-04-16 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Apr 16, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
936226955,9sleep10-21swapper/107:04:141
1097226651,8sleep00-21swapper/007:07:400
11295993939,0cyclictest0-21swapper/011:43:390
11295993613,3cyclictest0-21swapper/012:10:230
1129699320,31cyclictest0-21swapper/111:58:311
11295993110,8cyclictest0-21swapper/009:29:310
11296992929,0cyclictest0-21swapper/107:27:331
1129599290,24cyclictest0-21swapper/011:12:480
11295992710,6cyclictest0-21swapper/008:24:240
1129699261,24cyclictest0-21swapper/109:58:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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