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2026-04-01 - 11:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Mar 31, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2013527051,8sleep00-21swapper/007:08:430
1992827057,8sleep10-21swapper/107:06:351
21032680,0sleep00-21swapper/007:44:300
164532670,0sleep00-21swapper/010:14:070
115542640,0sleep111555-21sh10:05:531
288812500,0sleep10-21swapper/112:01:091
20367993632,3cyclictest12956-21if_eth012:24:311
20367993533,1cyclictest19531-21irqstats08:29:331
20367993532,2cyclictest3653-21apache_processe07:49:281
20367993532,2cyclictest32414-21df_inode07:39:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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