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2026-11-03 - 20:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Nov 03, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87327461,9sleep10-21swapper/107:05:591
3167426754,8sleep00-21swapper/007:02:350
1227993810,0cyclictest0-21swapper/112:07:441
1227993410,21cyclictest0-21swapper/112:33:421
1226992927,2cyclictest0-21swapper/009:42:550
1226992810,4cyclictest0-21swapper/012:17:320
1227992625,1cyclictest11036-21apache209:57:051
122799260,4cyclictest0-21swapper/110:03:291
1226992625,1cyclictest12135-1kworker/u5:011:20:370
1226992624,1cyclictest0-21swapper/009:28:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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