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2025-12-10 - 07:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Dec 10, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3005622120,1sleep00-21swapper/019:02:000
3058427057,8sleep10-21swapper/119:03:191
31086993910,28cyclictest0-21swapper/023:35:270
31087993310,3cyclictest0-21swapper/121:10:271
31086993310,17cyclictest0-21swapper/019:42:450
31086993014,6cyclictest7-21ksoftirqd/021:28:490
31086993010,0cyclictest0-21swapper/021:10:420
31087992928,1cyclictest0-21swapper/100:21:071
3108799280,23cyclictest0-21swapper/122:12:031
3108699287,20cyclictest0-21swapper/019:07:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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