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2026-02-19 - 06:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Feb 19, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324627449,8sleep00-21swapper/019:06:130
255727057,8sleep10-21swapper/119:04:541
113042650,0sleep10-21swapper/123:10:401
104002650,0sleep00-21swapper/020:49:490
3750993310,0cyclictest0-21swapper/122:09:581
3750993010,0cyclictest0-21swapper/123:35:091
3749993010,16cyclictest0-21swapper/022:01:070
3750992727,0cyclictest0-21swapper/121:12:181
3750992710,11cyclictest0-21swapper/122:52:251
3749992711,15cyclictest0-21swapper/022:56:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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