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2026-04-24 - 16:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Apr 24, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
457926957,8sleep00-21swapper/007:08:450
434626947,17sleep10-21swapper/107:06:211
4795993410,23cyclictest0-21swapper/109:46:031
479499310,30cyclictest0-21swapper/009:07:420
4794993010,2cyclictest0-21swapper/010:42:000
4794993010,13cyclictest0-21swapper/011:28:070
479599294,3cyclictest91rcu_preempt11:23:561
4795992924,2cyclictest24-21ksoftirqd/109:24:251
4795992828,0cyclictest0-21swapper/111:10:001
4795992810,0cyclictest0-21swapper/109:33:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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