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2025-09-15 - 12:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Sep 15, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35652730,0sleep00-21swapper/023:41:390
229552680,2sleep00-21swapper/022:37:270
1079726855,8sleep00-21swapper/019:05:370
1057726755,8sleep10-21swapper/119:03:191
140612650,0sleep10-21swapper/123:56:391
142032640,1sleep00-21swapper/020:42:230
73962620,0sleep10-21swapper/123:00:541
315002330,12sleep10-21swapper/119:57:351
11134993110,18cyclictest0-21swapper/019:41:270
1113499290,28cyclictest0-21swapper/022:16:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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