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2026-04-21 - 02:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Apr 20, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2405521180,1sleep02364599cyclictest12:36:290
50122710,0sleep10-21swapper/110:39:191
43522690,0sleep00-21swapper/011:24:080
2328226956,9sleep10-21swapper/107:07:131
2318026956,8sleep00-21swapper/007:06:100
23646994110,30cyclictest0-21swapper/110:47:141
23646993910,28cyclictest0-21swapper/109:29:401
23646993710,23cyclictest0-21swapper/108:29:191
23646993614,21cyclictest100150irq/106-eth1-rx10:08:181
23646993610,25cyclictest6641-21ssh09:54:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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