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2026-04-27 - 06:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Apr 27, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
474726956,8sleep10-21swapper/119:06:441
322726754,8sleep00-21swapper/019:04:140
5152993013,16cyclictest0-21swapper/019:36:500
5152992810,17cyclictest0-21swapper/023:36:200
515399270,7cyclictest8385-21grep23:39:211
5152992726,0cyclictest0-21swapper/021:56:190
415122710,14sleep10-21swapper/122:11:191
5153992626,0cyclictest0-21swapper/100:36:211
5153992625,0cyclictest0-21swapper/100:10:021
5153992619,4cyclictest0-21swapper/122:20:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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