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2026-06-29 - 11:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Jun 29, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90842770,0sleep09082-21seq20:28:480
995727050,15sleep10-21swapper/119:08:001
993627057,8sleep00-21swapper/019:07:470
118652670,1sleep10-21swapper/123:03:451
10190993020,2cyclictest0-21swapper/000:33:280
10190992910,0cyclictest0-21swapper/019:34:130
1019099284,4cyclictest91rcu_preempt23:03:500
1019099281,24cyclictest0-21swapper/021:37:430
1019099277,15cyclictest100150irq/106-eth1-rx22:48:440
1019099275,21cyclictest0-21swapper/000:16:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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