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2026-04-09 - 23:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Apr 09, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3193427461,9sleep00-21swapper/007:06:370
3180426755,8sleep10-21swapper/107:05:151
32364994210,31cyclictest20404-21ssh11:30:390
32364993910,14cyclictest0-21swapper/010:03:140
32364993815,10cyclictest91rcu_preempt12:21:550
32364993810,27cyclictest0-21swapper/010:09:280
32364993810,25cyclictest0-21swapper/008:09:240
32364993810,23cyclictest0-21swapper/011:19:240
32364993810,22cyclictest0-21swapper/008:06:000
32364993810,20cyclictest0-21swapper/011:25:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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