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2026-05-30 - 10:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat May 30, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1980727865,8sleep10-21swapper/119:05:261
47402710,0sleep10-21swapper/121:12:151
57382650,1sleep05731-21awk23:23:490
1990826553,8sleep00-21swapper/019:06:300
20310993710,26cyclictest0-21swapper/022:17:040
20311993535,0cyclictest0-21swapper/120:31:281
20311993520,14cyclictest31902-21kworker/1:223:42:361
20310993329,4cyclictest636-21nscd23:03:080
2031099293,6cyclictest0-21swapper/021:34:030
20311992826,1cyclictest0-21swapper/122:10:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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