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2025-12-13 - 22:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot2.osadl.org (updated Sat Dec 13, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
952526957,8sleep10-21swapper/107:07:261
935526856,8sleep00-21swapper/007:05:390
9950994110,30cyclictest0-21swapper/009:20:500
9950994110,30cyclictest0-21swapper/008:22:250
9950994010,10cyclictest0-21swapper/007:40:040
9950993910,29cyclictest0-21swapper/007:21:150
9950993910,27cyclictest0-21swapper/011:13:580
9950993810,28cyclictest0-21swapper/011:40:200
9950993810,27cyclictest0-21swapper/011:00:010
9950993810,27cyclictest0-21swapper/010:05:190
9950993810,27cyclictest0-21swapper/009:40:380
9950993810,26cyclictest0-21swapper/012:02:370
9950993710,27cyclictest0-21swapper/011:35:210
9950993710,27cyclictest0-21swapper/008:55:160
9950993710,26cyclictest0-21swapper/012:35:160
9950993710,26cyclictest0-21swapper/011:31:490
9950993710,26cyclictest0-21swapper/007:50:240
9950993610,25cyclictest0-21swapper/011:26:110
9950993610,25cyclictest0-21swapper/011:06:250
9950993610,25cyclictest0-21swapper/007:29:380
9950993610,23cyclictest0-21swapper/010:24:000
9950993510,25cyclictest0-21swapper/010:39:550
9950993510,24cyclictest0-21swapper/010:26:050
9950993510,24cyclictest0-21swapper/010:15:200
9950993510,24cyclictest0-21swapper/009:55:240
9950993510,24cyclictest0-21swapper/008:10:210
9950993510,21cyclictest0-21swapper/012:25:480
9950993510,19cyclictest0-21swapper/011:15:540
9950993410,5cyclictest0-21swapper/008:37:150
9950993410,23cyclictest0-21swapper/009:08:290
9950993310,7cyclictest0-21swapper/012:30:130
9950993310,5cyclictest0-21swapper/007:55:100
9950993310,23cyclictest0-21swapper/008:53:240
9950993310,22cyclictest0-21swapper/011:45:160
9950993310,22cyclictest0-21swapper/009:29:050
9950993310,22cyclictest0-21swapper/007:12:030
9950993310,20cyclictest0-21swapper/012:23:490
9950993210,21cyclictest0-21swapper/011:20:120
9950993210,21cyclictest0-21swapper/010:00:150
9950993110,20cyclictest0-21swapper/010:50:160
9950993110,18cyclictest0-21swapper/012:18:090
995199300,30cyclictest0-21swapper/109:53:031
9950993016,14cyclictest0-21swapper/008:00:420
9950993010,19cyclictest0-21swapper/011:00:200
9950993010,19cyclictest0-21swapper/007:32:230
9950993010,19cyclictest0-21swapper/007:17:170
9950993010,18cyclictest0-21swapper/007:47:130
995199290,24cyclictest15737-21/usr/sbin/munin07:25:151
9950992910,18cyclictest0-21swapper/008:27:570
9950992910,13cyclictest0-21swapper/009:30:200
9950992810,3cyclictest0-21swapper/011:50:150
9950992810,17cyclictest0-21swapper/008:05:180
995099273,23cyclictest0-21swapper/007:35:010
9950992715,12cyclictest0-21swapper/009:48:240
9950992710,3cyclictest0-21swapper/008:47:440
9950992710,17cyclictest0-21swapper/012:10:170
9950992710,16cyclictest0-21swapper/012:05:180
9950992710,16cyclictest0-21swapper/011:56:180
9950992710,16cyclictest0-21swapper/010:42:430
9950992710,16cyclictest0-21swapper/010:30:000
9950992710,16cyclictest0-21swapper/010:12:280
9950992710,16cyclictest0-21swapper/009:50:130
9950992710,10cyclictest0-21swapper/010:45:160
9951992624,1cyclictest24-21ksoftirqd/108:35:151
9951992523,1cyclictest24-21ksoftirqd/112:20:011
9951992513,4cyclictest0-21swapper/107:45:121
9950992510,8cyclictest0-21swapper/009:00:140
9950992510,14cyclictest0-21swapper/008:40:270
9950992410,4cyclictest0-21swapper/008:18:400
9950992410,1cyclictest0-21swapper/009:12:430
9950992410,13cyclictest0-21swapper/009:35:560
995199233,4cyclictest91rcu_preempt11:20:201
995199231,3cyclictest91rcu_preempt10:30:151
9951992310,6cyclictest0-21swapper/111:30:141
9951992310,5cyclictest0-21swapper/111:05:211
9951992310,10cyclictest0-21swapper/112:05:211
9950992310,10cyclictest0-21swapper/008:30:160
995199224,6cyclictest20892-21/usr/sbin/munin07:35:211
9951992220,1cyclictest32067-21ls08:05:171
9951992213,3cyclictest25051-21if_eth312:00:161
995199221,14cyclictest0-21swapper/109:10:241
995199221,11cyclictest26680-21switchtime07:50:211
9951992210,7cyclictest0-21swapper/111:00:141
995199220,10cyclictest0-21swapper/111:50:131
9950992210,11cyclictest0-21swapper/009:15:110
995199216,7cyclictest0-21swapper/108:45:131
995199215,9cyclictest0-21swapper/111:55:221
995199215,5cyclictest91rcu_preempt11:45:161
9951992121,0cyclictest24-21ksoftirqd/110:37:251
995199207,6cyclictest24-21ksoftirqd/108:50:541
9951992019,1cyclictest24-21ksoftirqd/110:55:201
995199201,3cyclictest0-21swapper/110:20:171
995199201,1cyclictest91rcu_preempt11:15:211
9951992010,8cyclictest0-21swapper/107:14:501
9951992010,5cyclictest28425-21proc_pri07:55:171
9951992010,3cyclictest0-21swapper/111:25:131
995199197,10cyclictest0-21swapper/109:30:171
995199196,9cyclictest0-21swapper/109:35:161
995199194,9cyclictest0-21swapper/110:10:211
995199194,11cyclictest0-21swapper/112:13:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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