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2026-02-04 - 03:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot2.osadl.org (updated Wed Feb 04, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
513528361,17sleep00-21swapper/019:05:340
57792780,0sleep10-21swapper/123:44:241
524727254,8sleep10-21swapper/119:06:451
73002700,1sleep17295-21unixbench_multi20:35:001
157412670,1sleep015740-21seq22:29:550
67772600,2sleep0570799cyclictest22:17:530
5707992927,1cyclictest0-21swapper/020:29:520
5710992828,0cyclictest0-21swapper/123:05:281
5710992825,2cyclictest770-21irqbalance21:10:211
571099280,14cyclictest0-21swapper/120:09:511
570799283,23cyclictest11505-21/usr/sbin/munin19:24:530
571099271,25cyclictest3304-21ssh22:13:361
5710992710,11cyclictest0-21swapper/100:22:411
570799270,4cyclictest91rcu_preempt19:29:570
5710992517,4cyclictest17429-21apache220:22:051
5710992510,5cyclictest0-21swapper/123:14:571
571099250,22cyclictest19457-21diskmemload21:43:221
570799255,17cyclictest7-21ksoftirqd/023:20:000
5707992510,9cyclictest0-21swapper/023:36:500
570799250,25cyclictest0-21swapper/023:43:380
571099242,21cyclictest0-21swapper/121:19:591
5710992410,9cyclictest0-21swapper/122:02:571
5710992410,6cyclictest0-21swapper/120:50:181
570799244,19cyclictest7-21ksoftirqd/000:24:520
570799244,11cyclictest21516-21apache_processe21:54:500
5707992423,0cyclictest7-21ksoftirqd/023:29:590
5707992418,3cyclictest81ktimersoftd/021:31:120
570799240,2cyclictest91rcu_preempt21:26:570
5710992321,1cyclictest0-21swapper/100:07:161
5710992320,1cyclictest0-21swapper/123:22:111
5710992317,3cyclictest17400-21apache222:52:241
5710992310,8cyclictest0-21swapper/122:09:401
5707992321,1cyclictest0-21swapper/021:46:580
5707992310,1cyclictest0-21swapper/023:25:290
5707992310,10cyclictest0-21swapper/021:54:360
5710992220,2cyclictest0-21swapper/120:44:231
5710992214,6cyclictest231ktimersoftd/123:32:581
5707992222,0cyclictest0-21swapper/000:38:040
570799222,16cyclictest100250irq/107-eth1-rx23:55:280
5707992219,1cyclictest7-21ksoftirqd/021:39:560
5707992210,6cyclictest0-21swapper/022:44:540
570799220,21cyclictest1034-21ntp_states22:09:570
571099216,11cyclictest0-21swapper/121:44:521
571099216,10cyclictest0-21swapper/123:55:021
5710992117,3cyclictest17400-21apache219:18:091
571099211,13cyclictest0-21swapper/100:30:511
571099210,15cyclictest0-21swapper/100:24:541
571099210,12cyclictest0-21swapper/122:35:001
5707992117,2cyclictest100150irq/106-eth1-rx00:04:340
5707992114,5cyclictest100150irq/106-eth1-rx00:07:420
5707992111,5cyclictest100150irq/106-eth1-rx23:44:510
5707992111,5cyclictest0-21swapper/021:14:210
5707992110,7cyclictest0-21swapper/023:10:210
5707992110,6cyclictest0-21swapper/022:24:570
5707992110,6cyclictest0-21swapper/019:09:530
5707992110,5cyclictest0-21swapper/019:39:500
5707992110,3cyclictest0-21swapper/023:00:180
347122110,0sleep00-21swapper/022:56:330
1103422110,0sleep00-21swapper/023:06:420
571099205,10cyclictest0-21swapper/119:35:011
571099202,15cyclictest0-21swapper/119:59:551
571099201,7cyclictest0-21swapper/119:49:571
5710992010,7cyclictest0-21swapper/122:47:451
5710992010,7cyclictest0-21swapper/121:49:511
5710992010,6cyclictest0-21swapper/121:32:111
5710992010,4cyclictest0-21swapper/121:24:561
5710992010,4cyclictest0-21swapper/100:01:321
5710992010,3cyclictest0-21swapper/122:19:581
5710992010,2cyclictest0-21swapper/121:14:591
571099200,2cyclictest0-21swapper/123:02:211
570799204,12cyclictest0-21swapper/022:43:110
570799204,10cyclictest0-21swapper/020:19:510
5707992018,1cyclictest7-21ksoftirqd/021:37:290
5707992010,5cyclictest0-21swapper/022:08:570
5707992010,4cyclictest0-21swapper/020:04:570
5707992010,4cyclictest0-21swapper/019:19:550
2634122010,0sleep00-21swapper/000:11:570
571099195,5cyclictest14821-21kworker/u4:100:36:511
5710991911,4cyclictest0-21swapper/123:34:541
5710991910,7cyclictest0-21swapper/122:54:561
5710991910,7cyclictest0-21swapper/100:09:431
5710991910,6cyclictest0-21swapper/119:23:511
5710991910,4cyclictest0-21swapper/122:24:511
570799198,8cyclictest0-21swapper/000:18:040
570799196,4cyclictest91rcu_preempt21:16:010
570799196,10cyclictest9900-21apache_volume23:49:520
570799195,5cyclictest0-21swapper/020:59:530
570799195,10cyclictest0-21swapper/021:19:500
570799193,7cyclictest0-21swapper/019:44:530
570799192,9cyclictest0-21swapper/020:09:580
5707991910,4cyclictest0-21swapper/023:18:080
5707991910,3cyclictest0-21swapper/022:04:200
1391121910,0sleep00-21swapper/020:54:570
571099187,4cyclictest636-21nscd22:29:451
571099183,15cyclictest0-21swapper/121:58:451
571099181,8cyclictest0-21swapper/100:17:241
5710991817,1cyclictest25079-21ssh22:42:311
5710991812,3cyclictest14113-21sh23:10:241
5710991811,1cyclictest4730-21/usr/sbin/munin22:14:581
5710991810,4cyclictest100150irq/106-eth1-rx21:00:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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