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2025-11-25 - 16:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot2.osadl.org (updated Tue Nov 25, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
731727147,19sleep00-21swapper/007:05:310
610127047,17sleep10-21swapper/107:02:021
99602600,0sleep10-21swapper/108:36:451
7614994210,9cyclictest0-21swapper/012:05:350
7614994210,31cyclictest0-21swapper/010:37:040
7614994210,31cyclictest0-21swapper/008:01:430
7614994210,22cyclictest91rcu_preempt12:17:370
7614994110,31cyclictest0-21swapper/008:55:350
7614994110,30cyclictest0-21swapper/011:10:070
7614994110,30cyclictest0-21swapper/008:43:140
7614994110,23cyclictest0-21swapper/007:41:460
7614994010,30cyclictest0-21swapper/009:59:200
7614994010,29cyclictest0-21swapper/010:23:510
7614994010,17cyclictest0-21swapper/011:36:490
7614993911,22cyclictest0-21swapper/009:01:460
7614993910,29cyclictest0-21swapper/007:52:020
7614993910,28cyclictest0-21swapper/012:11:540
7614993910,27cyclictest0-21swapper/009:38:520
7614993810,28cyclictest0-21swapper/011:05:320
7614993810,28cyclictest0-21swapper/010:09:430
7614993810,28cyclictest0-21swapper/009:10:370
7614993810,28cyclictest0-21swapper/008:28:530
7614993810,27cyclictest0-21swapper/010:32:290
7614993810,19cyclictest0-21swapper/010:12:010
7614993714,21cyclictest91rcu_preempt09:46:210
7614993710,27cyclictest0-21swapper/012:00:190
7614993710,27cyclictest0-21swapper/011:17:060
7614993710,27cyclictest0-21swapper/010:02:240
7614993710,27cyclictest0-21swapper/009:29:430
7614993710,27cyclictest0-21swapper/009:17:040
7614993710,26cyclictest0-21swapper/011:29:130
7614993710,26cyclictest0-21swapper/009:11:460
7614993710,26cyclictest0-21swapper/008:24:570
7614993710,22cyclictest0-21swapper/011:11:520
7614993710,19cyclictest91rcu_preempt07:06:570
761499370,36cyclictest10750-21sshd10:57:110
7615993610,1cyclictest0-21swapper/111:10:401
7614993610,24cyclictest91rcu_preempt07:35:420
7614993610,24cyclictest0-21swapper/011:46:590
7614993610,19cyclictest91rcu_preempt10:27:170
7614993610,16cyclictest0-21swapper/012:08:510
7615993510,9cyclictest0-21swapper/111:57:341
7614993512,23cyclictest12573-21ssh11:42:310
7614993510,25cyclictest0-21swapper/010:46:090
7614993510,24cyclictest0-21swapper/012:27:060
7614993410,24cyclictest0-21swapper/010:49:170
7614993410,23cyclictest0-21swapper/011:54:490
7614993410,23cyclictest0-21swapper/011:24:170
7614993410,18cyclictest91rcu_preempt09:54:250
7615993310,2cyclictest0-21swapper/109:32:041
7614993315,17cyclictest0-21swapper/011:32:030
7614993310,23cyclictest0-21swapper/012:34:350
761499330,32cyclictest0-21swapper/009:47:030
761499321,30cyclictest11474-21hddtemp_smartct10:16:570
761499321,30cyclictest10306-21ssh09:32:180
7614993210,7cyclictest0-21swapper/007:48:130
7614993210,22cyclictest0-21swapper/009:21:540
7614993210,22cyclictest0-21swapper/007:37:060
7614993210,20cyclictest0-21swapper/008:17:550
761499320,31cyclictest11198-21cat08:37:060
7615993110,15cyclictest0-21swapper/109:01:211
7614993116,14cyclictest0-21swapper/007:22:170
761499311,29cyclictest21484-21diskmemload10:53:590
7614993110,20cyclictest0-21swapper/008:46:580
7614993110,20cyclictest0-21swapper/008:10:530
7614993110,20cyclictest0-21swapper/007:12:190
7614993110,18cyclictest0-21swapper/007:28:520
761499310,30cyclictest11491-21apache_processe07:16:550
761599291,27cyclictest0-21swapper/111:18:481
761599290,28cyclictest0-21swapper/112:08:141
7614992910,18cyclictest0-21swapper/012:26:180
7615992811,4cyclictest0-21swapper/111:03:111
7615992810,1cyclictest0-21swapper/109:37:041
761499281,26cyclictest30383-21taskset08:02:350
761499281,26cyclictest0-21swapper/008:31:580
7615992715,9cyclictest0-21swapper/111:52:141
7615992710,16cyclictest0-21swapper/112:29:431
7615992710,14cyclictest0-21swapper/110:00:101
7615992610,15cyclictest0-21swapper/108:11:141
761599260,2cyclictest0-21swapper/111:30:001
7615992525,0cyclictest0-21swapper/109:29:121
7615992517,4cyclictest17445-21apache209:46:571
761599251,2cyclictest0-21swapper/109:23:011
7615992510,7cyclictest0-21swapper/110:37:011
7615992510,15cyclictest0-21swapper/108:28:111
761599250,2cyclictest0-21swapper/112:25:361
761499250,25cyclictest0-21swapper/008:11:450
7615992424,0cyclictest0-21swapper/110:12:241
7615992416,7cyclictest17445-21apache211:33:081
7615992410,4cyclictest0-21swapper/110:28:241
7615992410,2cyclictest0-21swapper/109:14:041
7615992410,0cyclictest0-21swapper/110:36:341
761599240,3cyclictest0-21swapper/112:17:381
761599240,2cyclictest0-21swapper/109:46:391
7615992318,3cyclictest0-21swapper/112:04:461
761599231,21cyclictest0-21swapper/111:26:191
7615992310,2cyclictest0-21swapper/109:16:441
761599222,12cyclictest0-21swapper/107:12:031
7615992221,1cyclictest0-21swapper/108:12:511
7615992220,1cyclictest0-21swapper/110:51:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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