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2026-05-07 - 16:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Thu May 07, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
896027146,21sleep00-21swapper/007:04:590
758527049,9sleep10-21swapper/107:04:021
299062640,0sleep00-21swapper/010:40:260
9526993229,2cyclictest10636-21kworker/u4:009:35:591
9526993210,22cyclictest0-21swapper/111:07:561
9526992927,1cyclictest231ktimersoftd/109:49:191
9526992910,3cyclictest0-21swapper/112:27:441
9525992928,1cyclictest0-21swapper/007:39:130
9526992826,1cyclictest32287-21/usr/sbin/munin10:44:131
9525992825,2cyclictest770-21irqbalance11:49:000
9525992810,1cyclictest0-21swapper/009:08:530
9526992717,3cyclictest7962-21ssh11:37:521
952599273,5cyclictest0-21swapper/009:37:480
9525992724,2cyclictest1199-21runrttasks10:52:280
9525992712,4cyclictest100150irq/106-eth1-rx11:15:200
9526992621,5cyclictest19426-21apache212:23:581
9525992625,0cyclictest7984-21kworker/u4:212:01:390
9526992510,0cyclictest0-21swapper/109:04:521
952599251,22cyclictest0-21swapper/010:58:090
9525992510,5cyclictest0-21swapper/011:09:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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