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2026-01-22 - 15:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Thu Jan 22, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
637326856,8sleep10-21swapper/107:06:171
670726654,8sleep00-21swapper/007:09:430
18682610,1sleep1231ktimersoftd/108:19:571
169012570,0sleep10-21swapper/111:17:391
12852540,0sleep10-21swapper/110:56:421
242332290,0sleep00-21swapper/009:57:550
6891992820,5cyclictest16772-21apache211:04:031
6890992626,0cyclictest0-21swapper/011:45:170
6891992510,9cyclictest0-21swapper/111:06:261
6891992510,8cyclictest0-21swapper/111:43:451
6890992524,1cyclictest81ktimersoftd/009:49:590
6890992519,4cyclictest16749-21apache211:19:440
6891992418,4cyclictest16749-21apache210:12:311
6891992417,6cyclictest17857-21ssh10:32:131
6891992410,5cyclictest0-21swapper/111:59:581
6891992410,0cyclictest0-21swapper/111:49:161
6891992410,0cyclictest0-21swapper/110:44:001
6890992422,1cyclictest0-21swapper/011:42:160
689099241,2cyclictest19309-21/usr/sbin/munin10:34:560
6891992319,1cyclictest1199-21runrttasks11:52:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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