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2025-08-21 - 22:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Thu Aug 21, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1852127057,8sleep10-21swapper/107:05:591
1842727058,8sleep00-21swapper/007:05:000
1884099336,25cyclictest28765-21apache209:49:351
18840993129,1cyclictest24-21ksoftirqd/112:17:251
18839993110,20cyclictest0-21swapper/012:10:220
18839993110,20cyclictest0-21swapper/009:50:070
18839993010,12cyclictest0-21swapper/011:42:380
18840992928,1cyclictest0-21swapper/110:37:591
18839992929,0cyclictest0-21swapper/008:02:100
1884099280,0cyclictest0-21swapper/111:02:481
1884099280,0cyclictest0-21swapper/109:10:491
18839992828,0cyclictest0-21swapper/009:39:290
18839992826,0cyclictest0-21swapper/009:23:490
1883999280,0cyclictest0-21swapper/011:56:270
1884099270,25cyclictest0-21swapper/110:09:351
18839992710,7cyclictest0-21swapper/010:51:460
1884099268,16cyclictest0-21swapper/110:25:361
1884099260,22cyclictest20099-21ssh11:38:491
18839992625,0cyclictest0-21swapper/009:36:570
1883999260,25cyclictest0-21swapper/008:13:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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