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2026-06-21 - 22:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sun Jun 21, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
938327650,8sleep00-21swapper/007:06:330
917426947,17sleep10-21swapper/107:04:211
146462650,0sleep014644-21seq12:33:550
186312640,0sleep10-21swapper/111:54:421
976599344,4cyclictest91rcu_preempt12:04:001
9765993317,5cyclictest24-21ksoftirqd/110:00:021
9765993311,10cyclictest91rcu_preempt11:01:471
9764993310,19cyclictest0-21swapper/011:24:200
976599324,3cyclictest91rcu_preempt09:35:511
976599324,2cyclictest91rcu_preempt11:33:521
976599324,0cyclictest91rcu_preempt11:05:391
9765993224,2cyclictest24-21ksoftirqd/107:23:381
9765993113,8cyclictest24-21ksoftirqd/110:56:571
9765993110,1cyclictest0-21swapper/110:23:531
976599309,2cyclictest91rcu_preempt12:09:481
976599307,2cyclictest91rcu_preempt08:30:481
9765993028,1cyclictest24-21ksoftirqd/110:38:561
9765993023,5cyclictest24-21ksoftirqd/109:23:561
9765993015,12cyclictest24-21ksoftirqd/110:32:531
976599299,3cyclictest91rcu_preempt09:50:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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