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2026-02-06 - 16:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Feb 06, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
662726653,8sleep00-21swapper/007:08:580
541626652,8sleep10-21swapper/107:04:571
290772660,1sleep10-21swapper/112:13:151
6875994341,1cyclictest7-21ksoftirqd/010:14:060
687599408,10cyclictest7-21ksoftirqd/010:24:580
687599399,6cyclictest7-21ksoftirqd/009:43:230
687599389,1cyclictest91rcu_preempt11:39:490
687599379,2cyclictest91rcu_preempt11:57:390
6875993736,0cyclictest7-21ksoftirqd/011:59:550
6875993617,3cyclictest91rcu_preempt11:18:490
6875993532,1cyclictest7-21ksoftirqd/010:04:580
6875993517,16cyclictest7-21ksoftirqd/011:27:360
6875993512,4cyclictest91rcu_preempt09:21:470
6875993512,3cyclictest91rcu_preempt09:35:460
6875993413,3cyclictest91rcu_preempt12:07:460
6876993310,22cyclictest0-21swapper/111:45:201
687599339,2cyclictest91rcu_preempt10:55:520
687599338,4cyclictest91rcu_preempt10:23:080
6875993321,6cyclictest13701-21ssh12:35:190
6875993316,4cyclictest91rcu_preempt08:39:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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