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2025-06-17 - 03:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Mon Jun 16, 2025 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69532720,1sleep16954-21ps08:13:171
1119626754,8sleep10-21swapper/107:03:081
1277126649,8sleep00-21swapper/007:06:100
244602640,0sleep10-21swapper/110:23:511
11822550,2sleep01312599cyclictest09:54:530
13125994110,30cyclictest0-21swapper/011:16:220
13125994110,30cyclictest0-21swapper/010:14:160
13125994110,30cyclictest0-21swapper/009:30:100
13125994110,30cyclictest0-21swapper/009:23:590
13125994110,30cyclictest0-21swapper/008:28:170
13125994010,30cyclictest0-21swapper/009:38:120
13125994010,29cyclictest0-21swapper/012:20:010
13125994010,29cyclictest0-21swapper/011:28:190
13125994010,29cyclictest0-21swapper/010:54:100
13125994010,28cyclictest7198-21ls08:13:180
13125994010,28cyclictest0-21swapper/009:51:140
13125994010,14cyclictest0-21swapper/012:24:350
13125993910,28cyclictest0-21swapper/012:13:260
13125993910,28cyclictest0-21swapper/012:08:120
13125993910,28cyclictest0-21swapper/011:39:300
13125993910,28cyclictest0-21swapper/011:33:450
13125993910,28cyclictest0-21swapper/010:39:450
13125993910,28cyclictest0-21swapper/008:34:130
13125993910,27cyclictest0-21swapper/009:35:170
13125993810,28cyclictest0-21swapper/010:08:130
13125993810,27cyclictest0-21swapper/011:43:230
13125993810,27cyclictest0-21swapper/009:20:560
13125993810,26cyclictest0-21swapper/008:58:150
13125993810,24cyclictest0-21swapper/011:07:360
13125993710,27cyclictest0-21swapper/012:05:440
13125993710,27cyclictest0-21swapper/007:33:120
13125993710,26cyclictest0-21swapper/010:26:380
13125993710,26cyclictest0-21swapper/010:01:240
13125993710,26cyclictest0-21swapper/009:46:380
13125993710,26cyclictest0-21swapper/009:08:550
13125993710,26cyclictest0-21swapper/007:53:170
13125993710,23cyclictest0-21swapper/011:23:330
13125993610,26cyclictest0-21swapper/012:33:280
13125993610,26cyclictest0-21swapper/011:11:220
13125993610,25cyclictest0-21swapper/011:48:180
13125993610,25cyclictest0-21swapper/009:16:140
13125993610,25cyclictest0-21swapper/008:38:200
13125993610,24cyclictest0-21swapper/008:26:030
13125993514,21cyclictest0-21swapper/011:59:220
13125993514,20cyclictest0-21swapper/010:59:360
13125993510,25cyclictest0-21swapper/010:20:450
13125993510,25cyclictest0-21swapper/007:58:110
13125993510,24cyclictest0-21swapper/010:46:150
13125993510,24cyclictest0-21swapper/010:34:370
13125993510,17cyclictest0-21swapper/008:50:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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