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2025-09-04 - 06:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Thu Sep 04, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2333123140,6sleep00-21swapper/019:02:380
1883521130,0sleep018834-21pidof20:16:460
2408427258,9sleep10-21swapper/119:04:451
24514993410,23cyclictest0-21swapper/022:49:020
24514993333,0cyclictest0-21swapper/021:09:130
24515993110,20cyclictest0-21swapper/100:10:001
24514993110,19cyclictest0-21swapper/023:29:590
24514993110,16cyclictest0-21swapper/023:27:080
24515992910,1cyclictest0-21swapper/121:48:051
24514992928,0cyclictest0-21swapper/000:04:070
24514992910,19cyclictest0-21swapper/020:52:040
24514992910,18cyclictest0-21swapper/022:31:320
24515992824,1cyclictest24-21ksoftirqd/121:12:381
24515992710,9cyclictest0-21swapper/123:50:421
2451599263,3cyclictest91rcu_preempt20:07:391
24515992624,1cyclictest32575-21ssh23:14:301
24515992624,1cyclictest0-21swapper/120:42:291
24515992610,2cyclictest0-21swapper/122:30:111
24514992626,0cyclictest0-21swapper/023:48:010
2451499261,24cyclictest0-21swapper/022:37:380
2451499261,22cyclictest0-21swapper/022:53:130
2451599254,20cyclictest0-21swapper/122:07:091
2451599253,4cyclictest91rcu_preempt22:43:031
24515992521,1cyclictest134-21jbd2/sda1-822:11:591
2451599251,3cyclictest91rcu_preempt20:52:391
24514992510,9cyclictest0-21swapper/022:02:370
2451599243,6cyclictest0-21swapper/121:22:281
24515992424,0cyclictest24-21ksoftirqd/121:57:201
24515992423,0cyclictest24-21ksoftirqd/123:59:371
24515992422,1cyclictest24-21ksoftirqd/100:17:361
24515992422,1cyclictest24-21ksoftirqd/100:16:061
24515992417,4cyclictest692-21ntpd22:01:261
24515992410,6cyclictest0-21swapper/122:19:471
2451599240,21cyclictest0-21swapper/123:03:341
2824522311,1sleep00-21swapper/023:07:540
2451599237,2cyclictest91rcu_preempt20:37:311
24515992321,1cyclictest24-21ksoftirqd/123:20:531
24515992321,1cyclictest18176-21apache222:13:461
24515992317,5cyclictest18176-21apache221:08:431
2451599230,3cyclictest91rcu_preempt21:37:341
2451499232,4cyclictest0-21swapper/020:27:190
24514992323,0cyclictest0-21swapper/019:41:060
2451499232,19cyclictest5718-21diskmemload21:20:290
24514992321,1cyclictest18176-21apache222:32:310
24514992321,1cyclictest16759-21/usr/sbin/munin22:07:350
24514992319,4cyclictest18176-21apache222:13:540
24514992310,8cyclictest0-21swapper/021:47:250
24514992310,4cyclictest0-21swapper/023:12:220
2451499230,16cyclictest0-21swapper/022:23:440
871822210,0sleep00-21swapper/000:12:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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