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2026-02-15 - 07:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Sun Feb 15, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1510827259,8sleep10-21swapper/119:07:431
1504226755,8sleep00-21swapper/019:07:000
15469993534,0cyclictest0-21swapper/020:23:480
1547099330,1cyclictest0-21swapper/121:45:541
1547099312,5cyclictest16824-21ssh21:34:521
15470993110,1cyclictest0-21swapper/121:03:431
15469993126,5cyclictest0-21swapper/022:57:170
1547099304,3cyclictest15706-21df19:09:521
15470993015,14cyclictest0-21swapper/120:49:471
15469992927,1cyclictest7-21ksoftirqd/021:09:360
15469992910,0cyclictest0-21swapper/000:31:200
1547099282,4cyclictest0-21swapper/120:44:521
1547099281,2cyclictest0-21swapper/121:04:481
15470992810,10cyclictest0-21swapper/123:12:001
15469992826,1cyclictest5662-21apache221:49:380
15469992810,10cyclictest0-21swapper/021:30:170
1546999280,27cyclictest0-21swapper/019:24:560
1547099273,5cyclictest30181-21grep21:09:531
1547099271,5cyclictest0-21swapper/123:37:391
1547099270,2cyclictest0-21swapper/123:24:571
15469992727,0cyclictest0-21swapper/022:52:120
1547099261,8cyclictest0-21swapper/119:52:271
1547099260,4cyclictest0-21swapper/123:59:591
15469992626,0cyclictest0-21swapper/023:26:060
15469992624,2cyclictest0-21swapper/022:01:130
1546999262,1cyclictest29386-21apache_processe00:04:480
1546999260,1cyclictest26361-21irqstats23:59:510
15470992523,1cyclictest636-21nscd23:04:451
15470992512,12cyclictest100150irq/106-eth1-rx22:55:481
15470992410,4cyclictest0-21swapper/121:17:501
1547099240,7cyclictest0-21swapper/122:07:581
1547099240,6cyclictest0-21swapper/121:50:121
1547099240,20cyclictest0-21swapper/119:27:211
15469992424,0cyclictest0-21swapper/000:39:230
15469992410,7cyclictest0-21swapper/022:04:510
1547099233,11cyclictest10412-21cron22:54:351
1547099231,9cyclictest0-21swapper/122:01:491
15470992314,4cyclictest15467-21cyclictest22:09:541
15470992312,6cyclictest0-21swapper/100:08:401
15470992310,5cyclictest0-21swapper/123:39:501
15470992310,5cyclictest0-21swapper/120:14:491
15470992310,1cyclictest0-21swapper/122:37:561
15470992310,11cyclictest100250irq/107-eth1-rx00:15:441
1547099230,9cyclictest0-21swapper/119:19:491
1547099230,6cyclictest10423-21ntp_states00:24:541
1547099230,13cyclictest0-21swapper/123:00:501
1546999237,7cyclictest25472-21/usr/sbin/munin20:59:540
15469992323,0cyclictest0-21swapper/021:35:240
15469992323,0cyclictest0-21swapper/021:12:450
15469992316,6cyclictest636-21nscd23:59:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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